a9025c58a4
fixes an issue with ARM APSR register handling: ( #1317 )
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- Q flag / GE flag were not included in APSR register (read/write)
- UC_ARM_REG_APSR_NZCV register constant was ignored completely.
- regression test added
2020-08-20 23:24:04 +08:00
690ada5f6a
Oss-fuzz ideal integration ( #1265 )
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* Adds oss-fuzz badge
* Generic fix for watchpoints leak
2020-05-23 09:59:30 +08:00
216c348c35
Oss-fuzz ideal integration ( #1262 )
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* Fix watchpoint leak in ARM
* Builds fuzz targets with sanitizer support
* Builds fuzz targets with directory driver
* Adds script to dowlonad public corpus
* Adds CIfuzz
To checks Pull Requests with fuzzing
* Use static library for fuzz targets
* Less verbose logs for fuzz driver directory
2020-05-21 16:15:12 +08:00
99097cab4c
Add implementation of access to the ARM SPSR register. ( #1178 )
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The SPSR register is named within the Unicorn headers, but the code
to access it is absent. This means that it will always read as 0 and
ignore writes. This makes it harder to work with changes in processor
mode, as the usual way to return from a CPU exception is a
`MOVS pc, lr` for undefined instructions or `SUBS pc, lr, #4`
for most other aborts - which implicitly restores the CPSR from SPSR.
This change adds the access to the SPSR so that it can be read and
written as the caller might expect.
2020-01-02 09:42:01 +08:00
ca6516ff79
Remove warnings ( #1140 )
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* remove warnings on windows with vs2019.
* remove warnings.
2019-09-08 16:44:16 +08:00
3185128031
Add ARM MSP, PSP and CONTROL register access ( #1071 )
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Necessary for NVIC exception emulation from user.
2019-03-07 08:37:27 +08:00
6c319941a5
Add support for the ARM IPSR register. ( #1067 )
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1. Create an enum name for the IPSR register.
2. Implement read and write of the IPSR via the xpsr helper functions.
Fixes #1065
2019-02-28 09:55:27 +08:00
094ca80092
fix conflicts
2017-03-30 12:23:24 +08:00
ccdb0ff523
armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.
2017-03-15 22:25:35 +08:00
d8fe34a2e8
armeb: Add support for ARM big endian.
2017-03-13 22:32:44 +08:00
c01dcf0a14
fix merge conflicts
2017-03-10 21:04:33 +08:00
0150ca24b1
Add support for ARM application flags - APSR register ( #776 )
2017-03-09 22:28:03 +08:00
6ea39f7d5a
merge msvc with master
2017-02-24 10:39:36 +08:00
053ecd7bf4
Added ARM coproc registers ( #684 )
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* Added ARM coproc registers
* Added regression test for vfp
2017-01-25 11:56:19 +08:00
8e45102b43
Arm support ported. ( #736 )
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* Fix for MIPS issue.
* Sparc support added.
* M68K support added.
* Arm support ported.
* Fix issue with VS2015 shlobj.h file
2017-01-23 23:30:57 +08:00
a63a34bfbc
Allow the client to write to CPSR
2017-01-05 00:00:15 +01:00
fccbcfd4c2
revert to use of g_free to make future qemu integrations easier ( #695 )
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* revert to use of g_free to make future qemu integrations easier
* bracing
2016-12-21 22:28:36 +08:00
e46545f722
remove glib dependency by provide compatible replacements
2016-12-18 14:56:58 -08:00
b7cdbe7a88
Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore
2016-10-07 09:57:07 +08:00
cb615fdba7
remove uc->cpus
2016-09-23 07:38:21 -07:00
0ef2b5fd71
New feature: registers can be bulk saved/restored in an opaque blob
2016-08-20 04:14:07 -07:00
fd39ec465b
arm: sync env.uc->thumb with env.thumb in arm_reg_write()
2016-07-30 13:21:44 +08:00
3a1c13fda9
Set thumb mode based on PC value in ARM. Mask off last bit of PC.
2016-06-17 13:46:34 +02:00
4b45869437
Reading and writing NEON registers
2016-05-04 11:23:32 +03:00
8932463f9d
arm: qutie emulation on EXCP_YIELD exception. this fixes testcase 004-segmentation_fault_1 in #520
2016-04-20 12:04:15 +08:00
cc6cbc5cf7
Merge branch 'memleak' into m2
2016-04-18 12:48:13 +08:00
acd88856e1
add batched reg access
2016-04-04 20:51:38 -07:00
fb1ebac000
Merge branch 'master' into m1
2016-03-09 15:13:42 +08:00
c5888e5670
move macros in qemu/target-*/unicorn*.c to uc_priv.h
2016-03-02 12:43:02 +09:00
1cd3c3093b
fix WRITE_BYTE_H
2016-03-02 10:51:50 +09:00
b69feb8d0b
Merge branch 'master' into memleak2
2016-02-15 15:52:10 +08:00
e73cbf1c88
arm: UC_QUERY_MODE return hardware mode (see issue #397 )
2016-02-06 09:47:57 +08:00
20b01a6933
fix merge conflict
2016-02-01 12:08:38 +08:00
36e53ad8a1
Fix arm & arm64 memleaks
2016-01-31 16:22:20 -06:00
c8569d8128
arm: fix change PC feature. now tests/regress/callback-pc.py passes
2016-01-28 16:03:19 +08:00
5a04bcb115
allow to change PC during callback. this solves issue #210
2016-01-28 14:06:17 +08:00
6f3d48077e
rename UC_QUERY_ARM_MODE to a more generic name UC_QUERY_MODE. make all bindings support this new constant
2016-01-24 01:08:23 +08:00
4dbad9aa9b
add new API uc_query() to query internal status of emulator at runtime
2016-01-23 17:14:44 +08:00
b4b83ff207
moar fixes
2016-01-23 12:56:47 +11:00
d8aaa2f44c
Fixes to runtime arm mask checks
2016-01-23 12:44:12 +11:00
678d645b80
Fix uc_mode usage in source code
2016-01-23 12:29:22 +11:00
8763d426c2
Fix uc_mode usage in source code
2016-01-23 12:08:49 +11:00
142d3a6f72
arm: allow to read CPSR register
2015-10-17 15:59:27 +08:00
3ac8615cbb
arm: handle invalid instruction. this fixes issue #114
2015-09-08 00:43:09 +08:00
84e3b5c897
cast all the values to write to registers in uc_reg_write() to unsigned type. this fixes issue #98
2015-09-04 11:17:08 +08:00
622d5cd5f9
change uch to uc_struct (target-arm)
2015-08-26 09:02:16 -04:00
9163bba812
restore mode of .[ch] files
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These were marked as executable in 5c3b6819http://stackoverflow.com/q/1580596/119527
2015-08-24 21:19:12 -04:00
5c3b681945
Add const to uc_reg_write and derivitives
2015-08-24 09:42:50 -07:00
a167f7c456
renames the register constants so unicorn and capstone can compile together
2015-08-23 21:36:33 -07:00
344d016104
import
2015-08-21 15:04:50 +08:00
