Commit Graph

690 Commits

Author SHA1 Message Date
mio
03f9dd8b61 Expand case ranges to build on MSVC 2021-12-30 00:42:13 +01:00
mio
dc402d78ec Ignore QEMU_BUILD_BUG_MSG on MSVC 2021-12-30 00:28:24 +01:00
mio
ab4ef2e1de Fix MSVC build and remove warning about unused functions 2021-12-30 00:26:25 +01:00
mio
298795a9f8 Fix build on MSVC 2021-12-29 23:18:49 +01:00
mio
034a1aa5f2 Make s390x stopping mechanism work 2021-12-27 23:48:20 +01:00
mio
a38151bf77 Make s390x skey work 2021-12-27 23:19:17 +01:00
mio
e977f81813 Make s390x build 2021-12-26 23:09:25 +01:00
mio
faa689c0f0 Merge systemz to the latest uc2 codebase 2021-12-26 22:58:32 +01:00
cddc9cf2ed Fix arm post init 2021-12-25 00:16:51 +01:00
4f73d75ea8 Fix #1500 2021-12-23 21:46:27 +01:00
ef6f8a2427 Fix x86 CPUID 2021-12-22 23:39:41 +01:00
7bb756249a Better design of cpuid instruction hook 2021-12-22 20:36:56 +01:00
63a445cbba fxsave / fxsave64 should store the floating point instruction pointer (fpip) (#1467)
* fxsave / fxsave64 should store the floating point instruction pointer (fpip)
- fxsave / fxsave64 happen to be used as GetPC code in exploits

* unit tests for the storage of FPIP in fxsave (x86) and fxsave64 (x64)
2021-12-13 08:40:32 +08:00
09b0c66f11 move all static vars in translate.c to tcg.h 2021-12-07 04:53:32 +08:00
4059906e78 Bug fix for LUI instruction (MIPS) 2021-12-06 19:15:00 +03:00
b042a6a01d add missing files 2021-12-06 04:28:13 +08:00
97b92d8861 initial systemz support 2021-12-06 04:19:37 +08:00
8a0ca8715e Fix SR read/write and a test 2021-12-04 23:22:28 +01:00
d204dc6374 Added SR to M68K reg_read and reg_write (#1507) 2021-12-02 14:12:49 +08:00
221cde18df Write CPSR as it is initiated from instructions to allow regs switch 2021-11-24 17:10:51 +01:00
78e0ddbc4d Fix mmio unmap 2021-11-24 00:18:19 +01:00
c733bbada3 Fix wrong offset used in split_region 2021-11-23 23:22:53 +01:00
c1c5f72918 Fix the sizemask for inline hooking 2021-11-23 21:18:21 +01:00
7a1de17f37 Fix UC_HOOK_EDGE_GENERATED to work with indirect jump
For an indirect jump (lookup_tb_ptr), last_tb would be NULL
2021-11-23 00:25:55 +01:00
083ccf160b Use fprintf 2021-11-22 21:22:21 +01:00
87a391d549 Inline uc_tracecode when there is only exactly one hook 2021-11-21 16:44:39 +01:00
c1106b811b Fix a memory leak in mmio 2021-11-16 22:44:03 +01:00
fc467edbc6 Fix 32bit target getting wrong offset for mmio 2021-11-16 22:40:57 +01:00
247ffbe0e8 Support nested uc_emu_start calls 2021-11-16 21:07:03 +01:00
43c643d4af Fix #1488 2021-11-16 09:41:21 +01:00
7e244f87b4 Fix UC_HOOK_EDGE_GENERATED implementation 2021-11-11 22:15:15 +01:00
23ef5da491 Merge pull request #1481 from bet4it/cp15
Restore cp15 registers
2021-11-09 16:50:31 +01:00
acaed986b5 Restore cp15 registers 2021-11-09 13:13:08 +08:00
640251e1aa Leave out size parameter in callback 2021-11-09 00:21:34 +01:00
2f61592ff9 Fix uc_mem_protect 2021-11-07 20:37:58 +01:00
c6fdbb3735 Add RISCV CSR registers 2021-11-07 20:36:04 +01:00
7268c2a19b mips: support reading and writing of hi/lo regs 2021-11-07 20:27:02 +01:00
94a82ed94d Ensure JIT protection is disabled when generating TB 2021-11-07 20:23:25 +01:00
613ddf0985 Format 2021-11-04 19:58:44 +01:00
871de4ad65 Split mips cpu to 32 and 64 2021-11-04 19:58:32 +01:00
0555095388 Support changing cpu model for ppc 2021-11-04 19:53:02 +01:00
e5a2eae173 Add comment for default cpu model 2021-11-04 19:22:50 +01:00
64452e249d Support changing cpu model for sparc 2021-11-04 19:22:08 +01:00
b0280f5e55 Support changing cpu model for m68k 2021-11-04 19:16:35 +01:00
172a2fbe6d Support changing cpu model for riscv 2021-11-04 19:13:53 +01:00
435ac71f47 Support changing cpu model for x86 2021-11-04 19:10:29 +01:00
837c3be347 Support changing cpu model for MIPS 2021-11-04 19:05:56 +01:00
dfbffa44ec Support changing cpu model for ARM 2021-11-04 18:37:10 +01:00
3e4b4af7d3 Support change page size 2021-11-04 17:03:30 +01:00
3ead1731fe Also instrument sub2
In this case, users don't need to care about the stuble difference inside tcg opcode
2021-11-03 23:48:09 +01:00