cf3451c37a
bindings: update ARM64 registers
2020-05-10 21:51:14 +08:00
625399774c
X64 base regs ( #1166 )
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* x86: setup FS & GS base
* Fixed base register writes for x64, removed then for x16/x32 (the don't exist there?)
* FS reg comes before GS so the base regs do so, too
* added shebang to const_generator.py
* Added base regs to and added 'all' support to const_generator
Co-authored-by: naq <aquynh@gmail.com >
2020-05-05 08:34:51 +08:00
b0d5837c61
bindings: add UC_ERR_TIMEOUT
2019-12-29 00:19:34 +08:00
3b17db0d84
bindings: update after the last commit on adding ARM modes
2019-10-26 05:02:39 +08:00
355eaecc12
bindings: update after addition of UC_HOOK_INSN_INVALID
2019-09-23 01:54:24 +08:00
24f55a7973
Removed hardcoded CP0C3_ULRI ( #1098 )
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* activate CP0C3_ULRI for CONFIG3, mips
* updated with mips patches
* updated with mips patches
* remove hardcoded config3
* git ignore vscode
* fix spacing issue and turn on floating point
2019-07-06 17:53:02 +08:00
07cafff76a
bindings: update for latest ARM registers addition
2019-03-07 08:38:41 +08:00
6d47b38b7f
bindings: update after recent addition of ARM_REG_IPSR
2019-02-28 09:56:29 +08:00
738d102989
bindings: add newly added register MXCSR
2019-02-15 13:01:27 +08:00
84220d8360
Pascal/Delphi binding ( #987 )
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* Pascal/Delphi binding
Pascal/Delphi language binding
* update credits
2018-08-03 20:33:25 +08:00
