c1c0baec7d
Fix IP value for UC_MODE_16 ( #1321 )
2020-09-10 10:02:22 +08:00
f988a41369
x86: support read/write to ST registers
2020-05-11 00:24:58 +08:00
625399774c
X64 base regs ( #1166 )
...
* x86: setup FS & GS base
* Fixed base register writes for x64, removed then for x16/x32 (the don't exist there?)
* FS reg comes before GS so the base regs do so, too
* added shebang to const_generator.py
* Added base regs to and added 'all' support to const_generator
Co-authored-by: naq <aquynh@gmail.com >
2020-05-05 08:34:51 +08:00
1eabe2ffaa
Fixes LM flag for CPUID extended feature mask ( #1202 )
2020-02-10 10:57:46 +08:00
c03f929c75
fix oss-fuzz issue 10334. ( #1149 )
2019-10-08 10:44:50 +08:00
23a426625f
check arguments, return error instead of raising exceptions. ( #1125 )
...
* check arguments, return error instaed of raising exceptions. close #1117 .
* remove empty lines. remove thr underscore prefix in function name.
2019-08-23 17:05:13 +08:00
ae6e3c193d
Fixes register reading and writing for XMM8-15 on x86-64 ( #1090 )
2019-06-03 19:04:41 +08:00
55d8d073bd
support for YMM registers ymm8-ymm15 ( #1079 )
2019-04-01 11:00:34 +08:00
256e7782ce
Added MXCSR register, fixed writing to FPUCW. ( #1059 )
...
* Added MXCSR register for reading and writing
* Changed writing for fpucw register, now the qemu rounding status is updated as well
2019-02-15 12:59:49 +08:00
536c4e77c4
i386: set MSR IA32_EFER to correct value at init for IA32e Mode ( #1047 )
2018-11-30 11:42:19 +08:00
a2493a0d41
[Fix] Fix a problem that use uc_reg_write to write fs, gs has no effets in x86 64-bit mode. ( #984 )
2018-11-10 21:24:11 +08:00
0f14c47344
Makes SYSENTER hookable again on x86 ( #996 )
...
Adds SYSENTER to the whitelist of supported hookable instructions in unicorn
as well as fixes up the existing sysenter_hook_x86 regression test which was
previously failing
Fixes unicorn-engine/unicorn#995
2018-08-09 23:32:31 +08:00
4d0157eb4a
x86: fix #968 . also fix potential bug of not clearing high bytes when updateing EIP
2018-07-26 15:19:23 +08:00
2a240079d8
[Fix] Add feature support for CMPXCHG16B instruction. ( #983 )
2018-07-25 15:00:41 +08:00
d7735487f7
Use the qemu helpers to get/set the x86 eflags ( #878 )
2017-09-15 22:18:38 +07:00
4b9efdc986
Adding INSN hook checks for x86 ( #833 )
...
* adding INSN hook checking for x86
* tabs to spaces
* need to return bool not uc_err
* fixed conditional after switching to bool
2017-05-14 00:16:17 +07:00
5385baba39
Implemented read and write access to the YMM registers ( #819 )
2017-05-05 09:02:58 +08:00
c01dcf0a14
fix merge conflicts
2017-03-10 21:04:33 +08:00
02e6c14e12
x86: add MSR API via reg API ( #755 )
...
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...
So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
Byte Value Size
0 MSR ID 4
4 MSR val 8
2017-02-24 21:37:19 +08:00
6ea39f7d5a
merge msvc with master
2017-02-24 10:39:36 +08:00
a03e908611
Fix initial state of segment registers ( #751 )
...
* Remove glib from samples makefile
* changes to 16 bit segment registers needs to update segment base as well as segment selector
* change how x86 segment registers are set in 16-bit mode
* more appropriate solution to initial state of x86 segment registers in 16-bit mode
* remove commented lines
2017-02-09 23:49:54 +08:00
f05984961b
Fix 16-bit address computations ( #747 )
...
* Remove glib from samples makefile
* changes to 16 bit segment registers needs to update segment base as well as segment selector
* change how x86 segment registers are set in 16-bit mode
2017-02-08 09:37:41 +08:00
770c5616e2
Automated leading tab to spaces conversion.
2017-01-21 12:28:22 +11:00
1aeaf5c40d
This code should now build the x86_x64-softmmu part 2.
2017-01-19 22:50:28 +11:00
fccbcfd4c2
revert to use of g_free to make future qemu integrations easier ( #695 )
...
* revert to use of g_free to make future qemu integrations easier
* bracing
2016-12-21 22:28:36 +08:00
e46545f722
remove glib dependency by provide compatible replacements
2016-12-18 14:56:58 -08:00
b7cdbe7a88
Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore
2016-10-07 09:57:07 +08:00
cb615fdba7
remove uc->cpus
2016-09-23 07:38:21 -07:00
0ef2b5fd71
New feature: registers can be bulk saved/restored in an opaque blob
2016-08-20 04:14:07 -07:00
4a8f52ae7f
support xmm registers
2016-08-09 19:34:34 -07:00
cc6cbc5cf7
Merge branch 'memleak' into m2
2016-04-18 12:48:13 +08:00
acd88856e1
add batched reg access
2016-04-04 20:51:38 -07:00
4c4203cec8
fix x86 segment setup by updating cached segment registers on reg_write
2016-03-22 23:54:30 -07:00
859111f8f5
x86: return immediately after handling FPSW/FPCW/FPTAG registers
2016-03-20 18:15:41 +08:00
fb1ebac000
Merge branch 'master' into m1
2016-03-09 15:13:42 +08:00
c5888e5670
move macros in qemu/target-*/unicorn*.c to uc_priv.h
2016-03-02 12:43:02 +09:00
1cd3c3093b
fix WRITE_BYTE_H
2016-03-02 10:51:50 +09:00
b69feb8d0b
Merge branch 'master' into memleak2
2016-02-15 15:52:10 +08:00
3bd7fa4bfe
chmod -x qemu/target-i386/unicorn.c
2016-02-12 13:48:58 +08:00
6478a24404
Merge branch 'gdt_idt' of https://github.com/cseagle/unicorn into cseagle-gdt_idt
2016-02-06 17:31:42 +08:00
dec3615d12
ldtr and tr limit is 20 bits, not 16 bits
2016-02-04 19:26:47 -08:00
b49358524f
fix reg_read casting for x86 segment registers
2016-02-04 19:22:39 -08:00
4cb43be5bf
fix reg_read casting for x86 segment registers
2016-02-04 19:20:59 -08:00
49b9f4f8da
uc_x86_mmr type available in qemu/target-i386/unicorn.c
2016-02-04 19:09:41 -08:00
c339ced218
file perms
2016-02-04 17:18:24 -08:00
f3dc2522a0
read/write of x86 segment registers should modify selector field not base field
2016-02-04 17:17:40 -08:00
59f7bf3be7
file perms
2016-02-04 16:48:27 -08:00
e59382e030
updated gdtr/idtr/ldtr/tr read/write code
2016-02-04 16:44:52 -08:00
9977054a15
add support for setting gdtr, idtr, ldtr, and tr programatically
2016-02-03 09:22:29 -08:00
20b01a6933
fix merge conflict
2016-02-01 12:08:38 +08:00
