8 Commits

Author	SHA1	Message	Date
Nguyen Anh Quynh	f36bd83f85	cleanup regress/sparc*.py	2015-09-16 15:46:10 +07:00
mothran	6962126707	update sparc_reg.py with %i registers	2015-09-14 23:28:09 -07:00
mothran	d1e19df64e	update the sparc_reg to test all g/o/l registers	2015-09-14 23:05:33 -07:00
mothran	69d73aa845	added emulated SPARC code for regress/sparc_reg.py, appears to be a bug in G and I registers	2015-09-14 21:23:42 -07:00
mothran	6b521e9e9b	update the sparc reg read/write to include o/l/i registers	2015-09-14 20:03:32 -07:00
Nguyen Anh Quynh	548355acca	sparc: do not accept BIGENDIAN mode in samples. more sanity check should be done in the core	2015-09-11 14:02:27 +08:00
Nguyen Anh Quynh	1724fabb05	add shebang for regress/sparc_reg.py	2015-09-08 09:14:22 +08:00
Ryan Hileman	5f6c475479	add regress for #126	2015-09-07 18:08:05 -07:00