8 Commits

Author	SHA1	Message	Date
lazymio	c4b4189857	Update bindings	2022-01-04 21:12:52 +01:00
lazymio	b9c0066a47	Format and naming	2021-11-04 20:04:57 +01:00
lazymio	090686f8ed	uc_ctl proposal (#1473) ... * Add uc_ctl * Add comments * Slightly changed for bindings generation * Generate bindings	2021-10-30 10:45:32 +08:00
Nguyen Anh Quynh	e8bd7ca087	bindings: update X86 register constants	2021-10-04 19:41:41 +08:00
Nguyen Anh Quynh	0a7223996d	bindings: update constants from ARM registers	2021-10-04 01:04:43 +08:00
Dominik Maier	625399774c	X64 base regs (#1166) ... * x86: setup FS & GS base * Fixed base register writes for x64, removed then for x16/x32 (the don't exist there?) * FS reg comes before GS so the base regs do so, too * added shebang to const_generator.py * Added base regs to and added 'all' support to const_generator Co-authored-by: naq <aquynh@gmail.com>	2020-05-05 08:34:51 +08:00
Nguyen Anh Quynh	738d102989	bindings: add newly added register MXCSR	2019-02-15 13:01:27 +08:00
Coldzer0	84220d8360	Pascal/Delphi binding (#987) ... * Pascal/Delphi binding Pascal/Delphi language binding * update credits	2018-08-03 20:33:25 +08:00