Commit Graph

9 Commits

Author SHA1 Message Date
625399774c X64 base regs (#1166)
* x86: setup FS & GS base

* Fixed base register writes for x64, removed then for x16/x32 (the don't exist there?)

* FS reg comes before GS so the base regs do so, too

* added shebang to const_generator.py

* Added base regs to and added 'all' support to const_generator

Co-authored-by: naq <aquynh@gmail.com>
2020-05-05 08:34:51 +08:00
738d102989 bindings: add newly added register MXCSR 2019-02-15 13:01:27 +08:00
02e6c14e12 x86: add MSR API via reg API (#755)
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...

So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
	Byte	Value		Size
	0	MSR ID		4
	4       MSR val		8
2017-02-24 21:37:19 +08:00
28b94d10b8 bindings: add X86 FPTAGS & FPCW registers after recent change in the core 2016-03-14 09:14:48 +08:00
0a3799eada FPU control word and tags 2016-03-09 19:14:33 -03:00
6986fa3947 x86: add new register enums for IDT, LDT, GDT & TR 2016-02-06 17:35:45 +08:00
60099d1d69 x86: add back 2 registers X86_REG_FCW & X86_REG_FPIP 2015-08-24 13:58:52 +08:00
a167f7c456 renames the register constants so unicorn and capstone can compile together 2015-08-23 21:36:33 -07:00
344d016104 import 2015-08-21 15:04:50 +08:00