9 Commits

Author	SHA1	Message	Date
Nguyen Anh Quynh	e8bd7ca087	bindings: update X86 register constants	2021-10-04 19:41:41 +08:00
Nguyen Anh Quynh	0a7223996d	bindings: update constants from ARM registers	2021-10-04 01:04:43 +08:00
Dominik Maier	625399774c	X64 base regs (#1166) ... * x86: setup FS & GS base * Fixed base register writes for x64, removed then for x16/x32 (the don't exist there?) * FS reg comes before GS so the base regs do so, too * added shebang to const_generator.py * Added base regs to and added 'all' support to const_generator Co-authored-by: naq <aquynh@gmail.com>	2020-05-05 08:34:51 +08:00
Nguyen Anh Quynh	738d102989	bindings: add newly added register MXCSR	2019-02-15 13:01:27 +08:00
Nguyen Anh Quynh	f4325f8c4e	bindings: update to support X86 MSR id	2017-02-24 21:51:01 +08:00
Nguyen Anh Quynh	28b94d10b8	bindings: add X86 FPTAGS & FPCW registers after recent change in the core	2016-03-14 09:14:48 +08:00
Nguyen Anh Quynh	6986fa3947	x86: add new register enums for IDT, LDT, GDT & TR	2016-02-06 17:35:45 +08:00
Chris Eagle	49f9f81079	First pass of const_generator still requires manual tweak of UC_MODE_BIG_ENDIAN	2015-08-28 19:43:45 -07:00
Chris Eagle	1a081c5ed8	Initial changes to support use of const_generator.py	2015-08-28 19:41:13 -07:00