// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT namespace UnicornManaged.Const open System [] module Riscv = // RISCV32 CPU let UC_CPU_RISCV32_ANY = 0 let UC_CPU_RISCV32_BASE32 = 1 let UC_CPU_RISCV32_SIFIVE_E31 = 2 let UC_CPU_RISCV32_SIFIVE_U34 = 3 // RISCV64 CPU let UC_CPU_RISCV64_ANY = 0 let UC_CPU_RISCV64_BASE64 = 1 let UC_CPU_RISCV64_SIFIVE_E51 = 2 let UC_CPU_RISCV64_SIFIVE_U54 = 3 // RISCV registers let UC_RISCV_REG_INVALID = 0 // General purpose registers let UC_RISCV_REG_X0 = 1 let UC_RISCV_REG_X1 = 2 let UC_RISCV_REG_X2 = 3 let UC_RISCV_REG_X3 = 4 let UC_RISCV_REG_X4 = 5 let UC_RISCV_REG_X5 = 6 let UC_RISCV_REG_X6 = 7 let UC_RISCV_REG_X7 = 8 let UC_RISCV_REG_X8 = 9 let UC_RISCV_REG_X9 = 10 let UC_RISCV_REG_X10 = 11 let UC_RISCV_REG_X11 = 12 let UC_RISCV_REG_X12 = 13 let UC_RISCV_REG_X13 = 14 let UC_RISCV_REG_X14 = 15 let UC_RISCV_REG_X15 = 16 let UC_RISCV_REG_X16 = 17 let UC_RISCV_REG_X17 = 18 let UC_RISCV_REG_X18 = 19 let UC_RISCV_REG_X19 = 20 let UC_RISCV_REG_X20 = 21 let UC_RISCV_REG_X21 = 22 let UC_RISCV_REG_X22 = 23 let UC_RISCV_REG_X23 = 24 let UC_RISCV_REG_X24 = 25 let UC_RISCV_REG_X25 = 26 let UC_RISCV_REG_X26 = 27 let UC_RISCV_REG_X27 = 28 let UC_RISCV_REG_X28 = 29 let UC_RISCV_REG_X29 = 30 let UC_RISCV_REG_X30 = 31 let UC_RISCV_REG_X31 = 32 // RISCV CSR let UC_RISCV_REG_USTATUS = 33 let UC_RISCV_REG_UIE = 34 let UC_RISCV_REG_UTVEC = 35 let UC_RISCV_REG_USCRATCH = 36 let UC_RISCV_REG_UEPC = 37 let UC_RISCV_REG_UCAUSE = 38 let UC_RISCV_REG_UTVAL = 39 let UC_RISCV_REG_UIP = 40 let UC_RISCV_REG_FFLAGS = 41 let UC_RISCV_REG_FRM = 42 let UC_RISCV_REG_FCSR = 43 let UC_RISCV_REG_CYCLE = 44 let UC_RISCV_REG_TIME = 45 let UC_RISCV_REG_INSTRET = 46 let UC_RISCV_REG_HPMCOUNTER3 = 47 let UC_RISCV_REG_HPMCOUNTER4 = 48 let UC_RISCV_REG_HPMCOUNTER5 = 49 let UC_RISCV_REG_HPMCOUNTER6 = 50 let UC_RISCV_REG_HPMCOUNTER7 = 51 let UC_RISCV_REG_HPMCOUNTER8 = 52 let UC_RISCV_REG_HPMCOUNTER9 = 53 let UC_RISCV_REG_HPMCOUNTER10 = 54 let UC_RISCV_REG_HPMCOUNTER11 = 55 let UC_RISCV_REG_HPMCOUNTER12 = 56 let UC_RISCV_REG_HPMCOUNTER13 = 57 let UC_RISCV_REG_HPMCOUNTER14 = 58 let UC_RISCV_REG_HPMCOUNTER15 = 59 let UC_RISCV_REG_HPMCOUNTER16 = 60 let UC_RISCV_REG_HPMCOUNTER17 = 61 let UC_RISCV_REG_HPMCOUNTER18 = 62 let UC_RISCV_REG_HPMCOUNTER19 = 63 let UC_RISCV_REG_HPMCOUNTER20 = 64 let UC_RISCV_REG_HPMCOUNTER21 = 65 let UC_RISCV_REG_HPMCOUNTER22 = 66 let UC_RISCV_REG_HPMCOUNTER23 = 67 let UC_RISCV_REG_HPMCOUNTER24 = 68 let UC_RISCV_REG_HPMCOUNTER25 = 69 let UC_RISCV_REG_HPMCOUNTER26 = 70 let UC_RISCV_REG_HPMCOUNTER27 = 71 let UC_RISCV_REG_HPMCOUNTER28 = 72 let UC_RISCV_REG_HPMCOUNTER29 = 73 let UC_RISCV_REG_HPMCOUNTER30 = 74 let UC_RISCV_REG_HPMCOUNTER31 = 75 let UC_RISCV_REG_CYCLEH = 76 let UC_RISCV_REG_TIMEH = 77 let UC_RISCV_REG_INSTRETH = 78 let UC_RISCV_REG_HPMCOUNTER3H = 79 let UC_RISCV_REG_HPMCOUNTER4H = 80 let UC_RISCV_REG_HPMCOUNTER5H = 81 let UC_RISCV_REG_HPMCOUNTER6H = 82 let UC_RISCV_REG_HPMCOUNTER7H = 83 let UC_RISCV_REG_HPMCOUNTER8H = 84 let UC_RISCV_REG_HPMCOUNTER9H = 85 let UC_RISCV_REG_HPMCOUNTER10H = 86 let UC_RISCV_REG_HPMCOUNTER11H = 87 let UC_RISCV_REG_HPMCOUNTER12H = 88 let UC_RISCV_REG_HPMCOUNTER13H = 89 let UC_RISCV_REG_HPMCOUNTER14H = 90 let UC_RISCV_REG_HPMCOUNTER15H = 91 let UC_RISCV_REG_HPMCOUNTER16H = 92 let UC_RISCV_REG_HPMCOUNTER17H = 93 let UC_RISCV_REG_HPMCOUNTER18H = 94 let UC_RISCV_REG_HPMCOUNTER19H = 95 let UC_RISCV_REG_HPMCOUNTER20H = 96 let UC_RISCV_REG_HPMCOUNTER21H = 97 let UC_RISCV_REG_HPMCOUNTER22H = 98 let UC_RISCV_REG_HPMCOUNTER23H = 99 let UC_RISCV_REG_HPMCOUNTER24H = 100 let UC_RISCV_REG_HPMCOUNTER25H = 101 let UC_RISCV_REG_HPMCOUNTER26H = 102 let UC_RISCV_REG_HPMCOUNTER27H = 103 let UC_RISCV_REG_HPMCOUNTER28H = 104 let UC_RISCV_REG_HPMCOUNTER29H = 105 let UC_RISCV_REG_HPMCOUNTER30H = 106 let UC_RISCV_REG_HPMCOUNTER31H = 107 let UC_RISCV_REG_MCYCLE = 108 let UC_RISCV_REG_MINSTRET = 109 let UC_RISCV_REG_MCYCLEH = 110 let UC_RISCV_REG_MINSTRETH = 111 let UC_RISCV_REG_MVENDORID = 112 let UC_RISCV_REG_MARCHID = 113 let UC_RISCV_REG_MIMPID = 114 let UC_RISCV_REG_MHARTID = 115 let UC_RISCV_REG_MSTATUS = 116 let UC_RISCV_REG_MISA = 117 let UC_RISCV_REG_MEDELEG = 118 let UC_RISCV_REG_MIDELEG = 119 let UC_RISCV_REG_MIE = 120 let UC_RISCV_REG_MTVEC = 121 let UC_RISCV_REG_MCOUNTEREN = 122 let UC_RISCV_REG_MSTATUSH = 123 let UC_RISCV_REG_MUCOUNTEREN = 124 let UC_RISCV_REG_MSCOUNTEREN = 125 let UC_RISCV_REG_MHCOUNTEREN = 126 let UC_RISCV_REG_MSCRATCH = 127 let UC_RISCV_REG_MEPC = 128 let UC_RISCV_REG_MCAUSE = 129 let UC_RISCV_REG_MTVAL = 130 let UC_RISCV_REG_MIP = 131 let UC_RISCV_REG_MBADADDR = 132 let UC_RISCV_REG_SSTATUS = 133 let UC_RISCV_REG_SEDELEG = 134 let UC_RISCV_REG_SIDELEG = 135 let UC_RISCV_REG_SIE = 136 let UC_RISCV_REG_STVEC = 137 let UC_RISCV_REG_SCOUNTEREN = 138 let UC_RISCV_REG_SSCRATCH = 139 let UC_RISCV_REG_SEPC = 140 let UC_RISCV_REG_SCAUSE = 141 let UC_RISCV_REG_STVAL = 142 let UC_RISCV_REG_SIP = 143 let UC_RISCV_REG_SBADADDR = 144 let UC_RISCV_REG_SPTBR = 145 let UC_RISCV_REG_SATP = 146 let UC_RISCV_REG_HSTATUS = 147 let UC_RISCV_REG_HEDELEG = 148 let UC_RISCV_REG_HIDELEG = 149 let UC_RISCV_REG_HIE = 150 let UC_RISCV_REG_HCOUNTEREN = 151 let UC_RISCV_REG_HTVAL = 152 let UC_RISCV_REG_HIP = 153 let UC_RISCV_REG_HTINST = 154 let UC_RISCV_REG_HGATP = 155 let UC_RISCV_REG_HTIMEDELTA = 156 let UC_RISCV_REG_HTIMEDELTAH = 157 // Floating-point registers let UC_RISCV_REG_F0 = 158 let UC_RISCV_REG_F1 = 159 let UC_RISCV_REG_F2 = 160 let UC_RISCV_REG_F3 = 161 let UC_RISCV_REG_F4 = 162 let UC_RISCV_REG_F5 = 163 let UC_RISCV_REG_F6 = 164 let UC_RISCV_REG_F7 = 165 let UC_RISCV_REG_F8 = 166 let UC_RISCV_REG_F9 = 167 let UC_RISCV_REG_F10 = 168 let UC_RISCV_REG_F11 = 169 let UC_RISCV_REG_F12 = 170 let UC_RISCV_REG_F13 = 171 let UC_RISCV_REG_F14 = 172 let UC_RISCV_REG_F15 = 173 let UC_RISCV_REG_F16 = 174 let UC_RISCV_REG_F17 = 175 let UC_RISCV_REG_F18 = 176 let UC_RISCV_REG_F19 = 177 let UC_RISCV_REG_F20 = 178 let UC_RISCV_REG_F21 = 179 let UC_RISCV_REG_F22 = 180 let UC_RISCV_REG_F23 = 181 let UC_RISCV_REG_F24 = 182 let UC_RISCV_REG_F25 = 183 let UC_RISCV_REG_F26 = 184 let UC_RISCV_REG_F27 = 185 let UC_RISCV_REG_F28 = 186 let UC_RISCV_REG_F29 = 187 let UC_RISCV_REG_F30 = 188 let UC_RISCV_REG_F31 = 189 let UC_RISCV_REG_PC = 190 let UC_RISCV_REG_ENDING = 191 // Alias registers let UC_RISCV_REG_ZERO = 1 let UC_RISCV_REG_RA = 2 let UC_RISCV_REG_SP = 3 let UC_RISCV_REG_GP = 4 let UC_RISCV_REG_TP = 5 let UC_RISCV_REG_T0 = 6 let UC_RISCV_REG_T1 = 7 let UC_RISCV_REG_T2 = 8 let UC_RISCV_REG_S0 = 9 let UC_RISCV_REG_FP = 9 let UC_RISCV_REG_S1 = 10 let UC_RISCV_REG_A0 = 11 let UC_RISCV_REG_A1 = 12 let UC_RISCV_REG_A2 = 13 let UC_RISCV_REG_A3 = 14 let UC_RISCV_REG_A4 = 15 let UC_RISCV_REG_A5 = 16 let UC_RISCV_REG_A6 = 17 let UC_RISCV_REG_A7 = 18 let UC_RISCV_REG_S2 = 19 let UC_RISCV_REG_S3 = 20 let UC_RISCV_REG_S4 = 21 let UC_RISCV_REG_S5 = 22 let UC_RISCV_REG_S6 = 23 let UC_RISCV_REG_S7 = 24 let UC_RISCV_REG_S8 = 25 let UC_RISCV_REG_S9 = 26 let UC_RISCV_REG_S10 = 27 let UC_RISCV_REG_S11 = 28 let UC_RISCV_REG_T3 = 29 let UC_RISCV_REG_T4 = 30 let UC_RISCV_REG_T5 = 31 let UC_RISCV_REG_T6 = 32 let UC_RISCV_REG_FT0 = 158 let UC_RISCV_REG_FT1 = 159 let UC_RISCV_REG_FT2 = 160 let UC_RISCV_REG_FT3 = 161 let UC_RISCV_REG_FT4 = 162 let UC_RISCV_REG_FT5 = 163 let UC_RISCV_REG_FT6 = 164 let UC_RISCV_REG_FT7 = 165 let UC_RISCV_REG_FS0 = 166 let UC_RISCV_REG_FS1 = 167 let UC_RISCV_REG_FA0 = 168 let UC_RISCV_REG_FA1 = 169 let UC_RISCV_REG_FA2 = 170 let UC_RISCV_REG_FA3 = 171 let UC_RISCV_REG_FA4 = 172 let UC_RISCV_REG_FA5 = 173 let UC_RISCV_REG_FA6 = 174 let UC_RISCV_REG_FA7 = 175 let UC_RISCV_REG_FS2 = 176 let UC_RISCV_REG_FS3 = 177 let UC_RISCV_REG_FS4 = 178 let UC_RISCV_REG_FS5 = 179 let UC_RISCV_REG_FS6 = 180 let UC_RISCV_REG_FS7 = 181 let UC_RISCV_REG_FS8 = 182 let UC_RISCV_REG_FS9 = 183 let UC_RISCV_REG_FS10 = 184 let UC_RISCV_REG_FS11 = 185 let UC_RISCV_REG_FT8 = 186 let UC_RISCV_REG_FT9 = 187 let UC_RISCV_REG_FT10 = 188 let UC_RISCV_REG_FT11 = 189