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favicon-trap/qemu/target/riscv
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lazymio 09aa0f944f Merge QDucasse:riscv_extension_d 
Fix and close #1469

Fix test for riscv float points

Fix the riscv cpu config we left out
2021-11-03 13:20:46 +01:00
..
insn_trans
import Unicorn2
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riscv32
import Unicorn2
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riscv64
import Unicorn2
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cpu_bits.h
import Unicorn2
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cpu_helper.c
import Unicorn2
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cpu_user.h
import Unicorn2
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cpu-param.h
import Unicorn2
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cpu.c
Merge QDucasse:riscv_extension_d
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cpu.h
import Unicorn2
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csr.c
import Unicorn2
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fpu_helper.c
import Unicorn2
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helper.h
Add a new hook type UC_HOOK_TCG_OPCODE
2021-11-03 01:46:24 +01:00
instmap.h
import Unicorn2
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op_helper.c
import Unicorn2
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pmp.c
import Unicorn2
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pmp.h
import Unicorn2
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README
import Unicorn2
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translate.c
Basic implementation of uc_ctl
2021-11-01 00:39:36 +01:00
unicorn.c
Add clang-format and format code to qemu code style
2021-10-29 12:44:49 +02:00
unicorn.h
Add clang-format and format code to qemu code style
2021-10-29 12:44:49 +02:00

README 

code under riscv32/ is from riscv32-softmmu/target/riscv/*.inc.c
code under riscv64/ is from riscv64-softmmu/target/riscv/*.inc.c

WARNING: these code are autogen from scripts/decodetree.py, DO NOT modify them.