322 lines
4.8 KiB
Rust
322 lines
4.8 KiB
Rust
#![allow(non_camel_case_types)]
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// ARM64 registers
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#[repr(C)]
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#[derive(PartialEq, Debug, Clone, Copy)]
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pub enum RegisterARM64 {
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INVALID = 0,
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X29 = 1,
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X30 = 2,
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NZCV = 3,
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SP = 4,
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WSP = 5,
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WZR = 6,
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XZR = 7,
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B0 = 8,
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B1 = 9,
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B2 = 10,
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B3 = 11,
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B4 = 12,
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B5 = 13,
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B6 = 14,
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B7 = 15,
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B8 = 16,
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B9 = 17,
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B10 = 18,
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B11 = 19,
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B12 = 20,
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B13 = 21,
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B14 = 22,
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B15 = 23,
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B16 = 24,
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B17 = 25,
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B18 = 26,
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B19 = 27,
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B20 = 28,
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B21 = 29,
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B22 = 30,
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B23 = 31,
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B24 = 32,
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B25 = 33,
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B26 = 34,
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B27 = 35,
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B28 = 36,
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B29 = 37,
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B30 = 38,
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B31 = 39,
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D0 = 40,
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D1 = 41,
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D2 = 42,
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D3 = 43,
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D4 = 44,
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D5 = 45,
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D6 = 46,
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D7 = 47,
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D8 = 48,
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D9 = 49,
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D10 = 50,
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D11 = 51,
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D12 = 52,
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D13 = 53,
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D14 = 54,
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D15 = 55,
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D16 = 56,
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D17 = 57,
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D18 = 58,
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D19 = 59,
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D20 = 60,
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D21 = 61,
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D22 = 62,
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D23 = 63,
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D24 = 64,
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D25 = 65,
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D26 = 66,
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D27 = 67,
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D28 = 68,
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D29 = 69,
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D30 = 70,
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D31 = 71,
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H0 = 72,
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H1 = 73,
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H2 = 74,
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H3 = 75,
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H4 = 76,
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H5 = 77,
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H6 = 78,
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H7 = 79,
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H8 = 80,
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H9 = 81,
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H10 = 82,
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H11 = 83,
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H12 = 84,
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H13 = 85,
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H14 = 86,
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H15 = 87,
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H16 = 88,
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H17 = 89,
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H18 = 90,
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H19 = 91,
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H20 = 92,
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H21 = 93,
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H22 = 94,
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H23 = 95,
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H24 = 96,
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H25 = 97,
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H26 = 98,
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H27 = 99,
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H28 = 100,
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H29 = 101,
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H30 = 102,
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H31 = 103,
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Q0 = 104,
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Q1 = 105,
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Q2 = 106,
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Q3 = 107,
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Q4 = 108,
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Q5 = 109,
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Q6 = 110,
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Q7 = 111,
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Q8 = 112,
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Q9 = 113,
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Q10 = 114,
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Q11 = 115,
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Q12 = 116,
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Q13 = 117,
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Q14 = 118,
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Q15 = 119,
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Q16 = 120,
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Q17 = 121,
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Q18 = 122,
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Q19 = 123,
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Q20 = 124,
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Q21 = 125,
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Q22 = 126,
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Q23 = 127,
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Q24 = 128,
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Q25 = 129,
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Q26 = 130,
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Q27 = 131,
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Q28 = 132,
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Q29 = 133,
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Q30 = 134,
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Q31 = 135,
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S0 = 136,
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S1 = 137,
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S2 = 138,
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S3 = 139,
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S4 = 140,
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S5 = 141,
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S6 = 142,
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S7 = 143,
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S8 = 144,
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S9 = 145,
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S10 = 146,
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S11 = 147,
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S12 = 148,
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S13 = 149,
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S14 = 150,
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S15 = 151,
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S16 = 152,
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S17 = 153,
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S18 = 154,
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S19 = 155,
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S20 = 156,
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S21 = 157,
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S22 = 158,
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S23 = 159,
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S24 = 160,
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S25 = 161,
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S26 = 162,
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S27 = 163,
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S28 = 164,
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S29 = 165,
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S30 = 166,
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S31 = 167,
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W0 = 168,
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W1 = 169,
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W2 = 170,
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W3 = 171,
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W4 = 172,
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W5 = 173,
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W6 = 174,
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W7 = 175,
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W8 = 176,
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W9 = 177,
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W10 = 178,
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W11 = 179,
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W12 = 180,
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W13 = 181,
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W14 = 182,
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W15 = 183,
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W16 = 184,
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W17 = 185,
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W18 = 186,
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W19 = 187,
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W20 = 188,
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W21 = 189,
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W22 = 190,
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W23 = 191,
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W24 = 192,
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W25 = 193,
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W26 = 194,
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W27 = 195,
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W28 = 196,
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W29 = 197,
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W30 = 198,
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X0 = 199,
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X1 = 200,
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X2 = 201,
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X3 = 202,
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X4 = 203,
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X5 = 204,
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X6 = 205,
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X7 = 206,
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X8 = 207,
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X9 = 208,
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X10 = 209,
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X11 = 210,
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X12 = 211,
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X13 = 212,
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X14 = 213,
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X15 = 214,
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X16 = 215,
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X17 = 216,
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X18 = 217,
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X19 = 218,
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X20 = 219,
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X21 = 220,
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X22 = 221,
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X23 = 222,
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X24 = 223,
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X25 = 224,
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X26 = 225,
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X27 = 226,
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X28 = 227,
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V0 = 228,
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V1 = 229,
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V2 = 230,
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V3 = 231,
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V4 = 232,
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V5 = 233,
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V6 = 234,
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V7 = 235,
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V8 = 236,
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V9 = 237,
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V10 = 238,
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V11 = 239,
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V12 = 240,
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V13 = 241,
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V14 = 242,
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V15 = 243,
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V16 = 244,
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V17 = 245,
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V18 = 246,
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V19 = 247,
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V20 = 248,
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V21 = 249,
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V22 = 250,
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V23 = 251,
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V24 = 252,
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V25 = 253,
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V26 = 254,
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V27 = 255,
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V28 = 256,
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V29 = 257,
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V30 = 258,
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V31 = 259,
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// pseudo registers
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PC = 260,
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CPACR_EL1 = 261,
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// thread registers
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TPIDR_EL0 = 262,
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TPIDRRO_EL0 = 263,
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TPIDR_EL1 = 264,
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PSTATE = 265,
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// exception link registers
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ELR_EL0 = 266,
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ELR_EL1 = 267,
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ELR_EL2 = 268,
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ELR_EL3 = 269,
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// stack pointers registers
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SP_EL0 = 270,
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SP_EL1 = 271,
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SP_EL2 = 272,
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SP_EL3 = 273,
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// other CP15 registers
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TTBR0_EL1 = 274,
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TTBR1_EL1 = 275,
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ESR_EL0 = 276,
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ESR_EL1 = 277,
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ESR_EL2 = 278,
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ESR_EL3 = 279,
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FAR_EL0 = 280,
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FAR_EL1 = 281,
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FAR_EL2 = 282,
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FAR_EL3 = 283,
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PAR_EL1 = 284,
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MAIR_EL1 = 285,
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VBAR_EL0 = 286,
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VBAR_EL1 = 287,
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VBAR_EL2 = 288,
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VBAR_EL3 = 289,
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ENDING = 290,
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// alias registers
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// (assoc) IP0 = 215,
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// (assoc) IP1 = 216,
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// (assoc) FP = 1,
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// (assoc) LR = 2,
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}
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impl RegisterARM64 {
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pub const IP0: RegisterARM64 = RegisterARM64::X16;
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pub const IP1: RegisterARM64 = RegisterARM64::X17;
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pub const FP: RegisterARM64 = RegisterARM64::X29;
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pub const LR: RegisterARM64 = RegisterARM64::X30;
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}
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