231 lines
5.1 KiB
C
231 lines
5.1 KiB
C
/* Unicorn Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015-2017 */
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/* This file is released under LGPL2.
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See COPYING.LGPL2 in root directory for more details
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*/
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#ifndef UNICORN_ARM_H
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#define UNICORN_ARM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _MSC_VER
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#pragma warning(disable : 4201)
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#endif
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//> ARM CPU
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typedef enum uc_cpu_arm {
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UC_CPU_ARM_926 = 0,
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UC_CPU_ARM_946,
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UC_CPU_ARM_1026,
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UC_CPU_ARM_1136_R2,
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UC_CPU_ARM_1136,
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UC_CPU_ARM_1176,
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UC_CPU_ARM_11MPCORE,
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UC_CPU_ARM_CORTEX_M0,
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UC_CPU_ARM_CORTEX_M3,
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UC_CPU_ARM_CORTEX_M4,
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UC_CPU_ARM_CORTEX_M7,
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UC_CPU_ARM_CORTEX_M33,
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UC_CPU_ARM_CORTEX_R5,
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UC_CPU_ARM_CORTEX_R5F,
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UC_CPU_ARM_CORTEX_A7,
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UC_CPU_ARM_CORTEX_A8,
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UC_CPU_ARM_CORTEX_A9,
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UC_CPU_ARM_CORTEX_A15,
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UC_CPU_ARM_TI925T,
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UC_CPU_ARM_SA1100,
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UC_CPU_ARM_SA1110,
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UC_CPU_ARM_PXA250,
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UC_CPU_ARM_PXA255,
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UC_CPU_ARM_PXA260,
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UC_CPU_ARM_PXA261,
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UC_CPU_ARM_PXA262,
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UC_CPU_ARM_PXA270,
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UC_CPU_ARM_PXA270A0,
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UC_CPU_ARM_PXA270A1,
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UC_CPU_ARM_PXA270B0,
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UC_CPU_ARM_PXA270B1,
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UC_CPU_ARM_PXA270C0,
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UC_CPU_ARM_PXA270C5,
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UC_CPU_ARM_MAX
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} uc_cpu_arm;
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// ARM coprocessor registers, use this with UC_ARM_REG_CP_REG to
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// in call to uc_reg_write/read() to access the registers.
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typedef struct uc_arm_cp_reg {
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int cp; // The coprocessor identifier
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int is64; // Is it a 64 bit control register
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int sec; // Security state
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int crn; // Coprocessor register number
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int crm; // Coprocessor register number
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int opc1; // Opcode1
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int opc2; // Opcode2
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uint64_t val; // The value to read/write
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} uc_arm_cp_reg;
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//> ARM registers
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typedef enum uc_arm_reg {
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UC_ARM_REG_INVALID = 0,
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UC_ARM_REG_APSR,
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UC_ARM_REG_APSR_NZCV,
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UC_ARM_REG_CPSR,
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UC_ARM_REG_FPEXC,
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UC_ARM_REG_FPINST,
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UC_ARM_REG_FPSCR,
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UC_ARM_REG_FPSCR_NZCV,
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UC_ARM_REG_FPSID,
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UC_ARM_REG_ITSTATE,
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UC_ARM_REG_LR,
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UC_ARM_REG_PC,
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UC_ARM_REG_SP,
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UC_ARM_REG_SPSR,
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UC_ARM_REG_D0,
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UC_ARM_REG_D1,
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UC_ARM_REG_D2,
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UC_ARM_REG_D3,
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UC_ARM_REG_D4,
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UC_ARM_REG_D5,
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UC_ARM_REG_D6,
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UC_ARM_REG_D7,
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UC_ARM_REG_D8,
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UC_ARM_REG_D9,
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UC_ARM_REG_D10,
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UC_ARM_REG_D11,
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UC_ARM_REG_D12,
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UC_ARM_REG_D13,
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UC_ARM_REG_D14,
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UC_ARM_REG_D15,
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UC_ARM_REG_D16,
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UC_ARM_REG_D17,
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UC_ARM_REG_D18,
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UC_ARM_REG_D19,
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UC_ARM_REG_D20,
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UC_ARM_REG_D21,
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UC_ARM_REG_D22,
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UC_ARM_REG_D23,
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UC_ARM_REG_D24,
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UC_ARM_REG_D25,
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UC_ARM_REG_D26,
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UC_ARM_REG_D27,
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UC_ARM_REG_D28,
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UC_ARM_REG_D29,
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UC_ARM_REG_D30,
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UC_ARM_REG_D31,
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UC_ARM_REG_FPINST2,
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UC_ARM_REG_MVFR0,
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UC_ARM_REG_MVFR1,
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UC_ARM_REG_MVFR2,
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UC_ARM_REG_Q0,
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UC_ARM_REG_Q1,
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UC_ARM_REG_Q2,
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UC_ARM_REG_Q3,
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UC_ARM_REG_Q4,
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UC_ARM_REG_Q5,
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UC_ARM_REG_Q6,
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UC_ARM_REG_Q7,
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UC_ARM_REG_Q8,
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UC_ARM_REG_Q9,
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UC_ARM_REG_Q10,
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UC_ARM_REG_Q11,
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UC_ARM_REG_Q12,
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UC_ARM_REG_Q13,
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UC_ARM_REG_Q14,
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UC_ARM_REG_Q15,
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UC_ARM_REG_R0,
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UC_ARM_REG_R1,
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UC_ARM_REG_R2,
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UC_ARM_REG_R3,
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UC_ARM_REG_R4,
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UC_ARM_REG_R5,
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UC_ARM_REG_R6,
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UC_ARM_REG_R7,
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UC_ARM_REG_R8,
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UC_ARM_REG_R9,
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UC_ARM_REG_R10,
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UC_ARM_REG_R11,
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UC_ARM_REG_R12,
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UC_ARM_REG_S0,
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UC_ARM_REG_S1,
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UC_ARM_REG_S2,
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UC_ARM_REG_S3,
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UC_ARM_REG_S4,
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UC_ARM_REG_S5,
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UC_ARM_REG_S6,
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UC_ARM_REG_S7,
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UC_ARM_REG_S8,
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UC_ARM_REG_S9,
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UC_ARM_REG_S10,
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UC_ARM_REG_S11,
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UC_ARM_REG_S12,
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UC_ARM_REG_S13,
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UC_ARM_REG_S14,
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UC_ARM_REG_S15,
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UC_ARM_REG_S16,
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UC_ARM_REG_S17,
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UC_ARM_REG_S18,
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UC_ARM_REG_S19,
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UC_ARM_REG_S20,
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UC_ARM_REG_S21,
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UC_ARM_REG_S22,
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UC_ARM_REG_S23,
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UC_ARM_REG_S24,
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UC_ARM_REG_S25,
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UC_ARM_REG_S26,
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UC_ARM_REG_S27,
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UC_ARM_REG_S28,
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UC_ARM_REG_S29,
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UC_ARM_REG_S30,
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UC_ARM_REG_S31,
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UC_ARM_REG_C1_C0_2, // Depreciated, use UC_ARM_REG_CP_REG instead
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UC_ARM_REG_C13_C0_2, // Depreciated, use UC_ARM_REG_CP_REG instead
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UC_ARM_REG_C13_C0_3, // Depreciated, use UC_ARM_REG_CP_REG instead
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UC_ARM_REG_IPSR,
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UC_ARM_REG_MSP,
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UC_ARM_REG_PSP,
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UC_ARM_REG_CONTROL,
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UC_ARM_REG_IAPSR,
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UC_ARM_REG_EAPSR,
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UC_ARM_REG_XPSR,
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UC_ARM_REG_EPSR,
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UC_ARM_REG_IEPSR,
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UC_ARM_REG_PRIMASK,
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UC_ARM_REG_BASEPRI,
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UC_ARM_REG_BASEPRI_MAX,
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UC_ARM_REG_FAULTMASK,
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UC_ARM_REG_APSR_NZCVQ,
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UC_ARM_REG_APSR_G,
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UC_ARM_REG_APSR_NZCVQG,
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UC_ARM_REG_IAPSR_NZCVQ,
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UC_ARM_REG_IAPSR_G,
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UC_ARM_REG_IAPSR_NZCVQG,
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UC_ARM_REG_EAPSR_NZCVQ,
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UC_ARM_REG_EAPSR_G,
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UC_ARM_REG_EAPSR_NZCVQG,
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UC_ARM_REG_XPSR_NZCVQ,
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UC_ARM_REG_XPSR_G,
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UC_ARM_REG_XPSR_NZCVQG,
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UC_ARM_REG_CP_REG,
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UC_ARM_REG_ENDING, // <-- mark the end of the list or registers
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//> alias registers
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UC_ARM_REG_R13 = UC_ARM_REG_SP,
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UC_ARM_REG_R14 = UC_ARM_REG_LR,
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UC_ARM_REG_R15 = UC_ARM_REG_PC,
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UC_ARM_REG_SB = UC_ARM_REG_R9,
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UC_ARM_REG_SL = UC_ARM_REG_R10,
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UC_ARM_REG_FP = UC_ARM_REG_R11,
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UC_ARM_REG_IP = UC_ARM_REG_R12,
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} uc_arm_reg;
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#ifdef __cplusplus
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}
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#endif
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#endif
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