59fb8a2733
The addition of these registers in the C base caused the rust values for all floating point registers and the PC to point to some of the CSR registers instead.
347 lines
8.8 KiB
Rust
347 lines
8.8 KiB
Rust
#![allow(non_camel_case_types)]
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
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// RISCV registers
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#[repr(C)]
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#[derive(PartialEq, Debug, Clone, Copy)]
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pub enum RegisterRISCV {
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INVALID = 0,
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// General purpose registers
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X0 = 1,
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X1 = 2,
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X2 = 3,
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X3 = 4,
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X4 = 5,
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X5 = 6,
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X6 = 7,
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X7 = 8,
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X8 = 9,
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X9 = 10,
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X10 = 11,
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X11 = 12,
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X12 = 13,
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X13 = 14,
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X14 = 15,
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X15 = 16,
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X16 = 17,
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X17 = 18,
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X18 = 19,
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X19 = 20,
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X20 = 21,
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X21 = 22,
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X22 = 23,
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X23 = 24,
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X24 = 25,
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X25 = 26,
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X26 = 27,
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X27 = 28,
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X28 = 29,
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X29 = 30,
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X30 = 31,
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X31 = 32,
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// CSR
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USTATUS = 33,
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UIE = 34,
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UTVEC = 35,
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USCRATCH = 36,
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UEPC = 37,
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UCAUSE = 38,
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UTVAL = 39,
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UIP = 40,
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FFLAGS = 41,
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FRM = 42,
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FCSR = 43,
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CYCLE = 44,
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TIME = 45,
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INSTRET = 46,
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HPMCOUNTER3 = 47,
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HPMCOUNTER4 = 48,
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HPMCOUNTER5 = 49,
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HPMCOUNTER6 = 50,
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HPMCOUNTER7 = 51,
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HPMCOUNTER8 = 52,
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HPMCOUNTER9 = 53,
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HPMCOUNTER10 = 54,
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HPMCOUNTER11 = 55,
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HPMCOUNTER12 = 56,
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HPMCOUNTER13 = 57,
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HPMCOUNTER14 = 58,
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HPMCOUNTER15 = 59,
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HPMCOUNTER16 = 60,
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HPMCOUNTER17 = 61,
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HPMCOUNTER18 = 62,
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HPMCOUNTER19 = 63,
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HPMCOUNTER20 = 64,
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HPMCOUNTER21 = 65,
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HPMCOUNTER22 = 66,
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HPMCOUNTER23 = 67,
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HPMCOUNTER24 = 68,
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HPMCOUNTER25 = 69,
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HPMCOUNTER26 = 70,
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HPMCOUNTER27 = 71,
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HPMCOUNTER28 = 72,
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HPMCOUNTER29 = 73,
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HPMCOUNTER30 = 74,
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HPMCOUNTER31 = 75,
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CYCLEH = 76,
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TIMEH = 77,
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INSTRETH = 78,
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HPMCOUNTER3H = 79,
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HPMCOUNTER4H = 80,
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HPMCOUNTER5H = 81,
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HPMCOUNTER6H = 82,
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HPMCOUNTER7H = 83,
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HPMCOUNTER8H = 84,
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HPMCOUNTER9H = 85,
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HPMCOUNTER10H = 86,
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HPMCOUNTER11H = 87,
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HPMCOUNTER12H = 88,
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HPMCOUNTER13H = 89,
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HPMCOUNTER14H = 90,
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HPMCOUNTER15H = 91,
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HPMCOUNTER16H = 92,
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HPMCOUNTER17H = 93,
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HPMCOUNTER18H = 94,
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HPMCOUNTER19H = 95,
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HPMCOUNTER20H = 96,
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HPMCOUNTER21H = 97,
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HPMCOUNTER22H = 98,
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HPMCOUNTER23H = 99,
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HPMCOUNTER24H = 100,
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HPMCOUNTER25H = 101,
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HPMCOUNTER26H = 102,
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HPMCOUNTER27H = 103,
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HPMCOUNTER28H = 104,
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HPMCOUNTER29H = 105,
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HPMCOUNTER30H = 106,
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HPMCOUNTER31H = 107,
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MCYCLE = 108,
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MINSTRET = 109,
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MCYCLEH = 110,
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MINSTRETH = 111,
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MVENDORID = 112,
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MARCHID = 113,
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MIMPID = 114,
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MHARTID = 115,
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MSTATUS = 116,
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MISA = 117,
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MEDELEG = 118,
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MIDELEG = 119,
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MIE = 120,
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MTVEC = 121,
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MCOUNTEREN = 122,
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MSTATUSH = 123,
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MUCOUNTEREN = 124,
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MSCOUNTEREN = 125,
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MHCOUNTEREN = 126,
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MSCRATCH = 127,
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MEPC = 128,
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MCAUSE = 129,
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MTVAL = 130,
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MIP = 131,
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MBADADDR = 132,
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SSTATUS = 133,
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SEDELEG = 134,
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SIDELEG = 135,
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SIE = 136,
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STVEC = 137,
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SCOUNTEREN = 138,
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SSCRATCH = 139,
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SEPC = 140,
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SCAUSE = 141,
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STVAL = 142,
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SIP = 143,
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SBADADDR = 144,
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SPTBR = 145,
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SATP = 146,
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HSTATUS = 147,
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HEDELEG = 148,
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HIDELEG = 149,
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HIE = 150,
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HCOUNTEREN = 151,
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HTVAL = 152,
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HIP = 153,
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HTINST = 154,
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HGATP = 155,
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HTIMEDELTA = 156,
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HTIMEDELTAH = 157,
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// Floating-point registers
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F0 = 158,
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F1 = 159,
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F2 = 160,
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F3 = 161,
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F4 = 162,
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F5 = 163,
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F6 = 164,
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F7 = 165,
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F8 = 166,
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F9 = 167,
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F10 = 168,
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F11 = 169,
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F12 = 170,
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F13 = 171,
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F14 = 172,
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F15 = 173,
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F16 = 174,
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F17 = 175,
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F18 = 176,
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F19 = 177,
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F20 = 178,
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F21 = 179,
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F22 = 180,
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F23 = 181,
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F24 = 182,
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F25 = 183,
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F26 = 184,
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F27 = 185,
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F28 = 186,
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F29 = 187,
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F30 = 188,
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F31 = 189,
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PC = 190,
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ENDING = 191,
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}
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impl RegisterRISCV {
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// Alias registers
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// (assoc) ZERO = 1,
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// (assoc) RA = 2,
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// (assoc) SP = 3,
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// (assoc) GP = 4,
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// (assoc) TP = 5,
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// (assoc) T0 = 6,
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// (assoc) T1 = 7,
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// (assoc) T2 = 8,
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// (assoc) S0 = 9,
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// (assoc) FP = 9,
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// (assoc) S1 = 10,
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// (assoc) A0 = 11,
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// (assoc) A1 = 12,
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// (assoc) A2 = 13,
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// (assoc) A3 = 14,
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// (assoc) A4 = 15,
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// (assoc) A5 = 16,
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// (assoc) A6 = 17,
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// (assoc) A7 = 18,
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// (assoc) S2 = 19,
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// (assoc) S3 = 20,
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// (assoc) S4 = 21,
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// (assoc) S5 = 22,
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// (assoc) S6 = 23,
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// (assoc) S7 = 24,
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// (assoc) S8 = 25,
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// (assoc) S9 = 26,
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// (assoc) S10 = 27,
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// (assoc) S11 = 28,
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// (assoc) T3 = 29,
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// (assoc) T4 = 30,
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// (assoc) T5 = 31,
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// (assoc) T6 = 32,
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// (assoc) FT0 = 33,
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// (assoc) FT1 = 34,
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// (assoc) FT2 = 35,
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// (assoc) FT3 = 36,
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// (assoc) FT4 = 37,
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// (assoc) FT5 = 38,
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// (assoc) FT6 = 39,
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// (assoc) FT7 = 40,
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// (assoc) FS0 = 41,
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// (assoc) FS1 = 42,
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// (assoc) FA0 = 43,
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// (assoc) FA1 = 44,
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// (assoc) FA2 = 45,
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// (assoc) FA3 = 46,
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// (assoc) FA4 = 47,
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// (assoc) FA5 = 48,
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// (assoc) FA6 = 49,
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// (assoc) FA7 = 50,
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// (assoc) FS2 = 51,
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// (assoc) FS3 = 52,
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// (assoc) FS4 = 53,
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// (assoc) FS5 = 54,
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// (assoc) FS6 = 55,
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// (assoc) FS7 = 56,
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// (assoc) FS8 = 57,
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// (assoc) FS9 = 58,
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// (assoc) FS10 = 59,
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// (assoc) FS11 = 60,
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// (assoc) FT8 = 61,
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// (assoc) FT9 = 62,
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// (assoc) FT10 = 63,
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// (assoc) FT11 = 64,
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pub const ZERO: RegisterRISCV = RegisterRISCV::X0;
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pub const RA: RegisterRISCV = RegisterRISCV::X1;
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pub const SP: RegisterRISCV = RegisterRISCV::X2;
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pub const GP: RegisterRISCV = RegisterRISCV::X3;
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pub const TP: RegisterRISCV = RegisterRISCV::X4;
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pub const T0: RegisterRISCV = RegisterRISCV::X5;
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pub const T1: RegisterRISCV = RegisterRISCV::X6;
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pub const T2: RegisterRISCV = RegisterRISCV::X7;
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pub const S0: RegisterRISCV = RegisterRISCV::X8;
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pub const FP: RegisterRISCV = RegisterRISCV::X8;
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pub const S1: RegisterRISCV = RegisterRISCV::X9;
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pub const A0: RegisterRISCV = RegisterRISCV::X10;
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pub const A1: RegisterRISCV = RegisterRISCV::X11;
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pub const A2: RegisterRISCV = RegisterRISCV::X12;
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pub const A3: RegisterRISCV = RegisterRISCV::X13;
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pub const A4: RegisterRISCV = RegisterRISCV::X14;
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pub const A5: RegisterRISCV = RegisterRISCV::X15;
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pub const A6: RegisterRISCV = RegisterRISCV::X16;
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pub const A7: RegisterRISCV = RegisterRISCV::X17;
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pub const S2: RegisterRISCV = RegisterRISCV::X18;
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pub const S3: RegisterRISCV = RegisterRISCV::X19;
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pub const S4: RegisterRISCV = RegisterRISCV::X20;
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pub const S5: RegisterRISCV = RegisterRISCV::X21;
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pub const S6: RegisterRISCV = RegisterRISCV::X22;
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pub const S7: RegisterRISCV = RegisterRISCV::X23;
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pub const S8: RegisterRISCV = RegisterRISCV::X24;
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pub const S9: RegisterRISCV = RegisterRISCV::X25;
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pub const S10: RegisterRISCV = RegisterRISCV::X26;
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pub const S11: RegisterRISCV = RegisterRISCV::X27;
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pub const T3: RegisterRISCV = RegisterRISCV::X28;
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pub const T4: RegisterRISCV = RegisterRISCV::X29;
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pub const T5: RegisterRISCV = RegisterRISCV::X30;
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pub const T6: RegisterRISCV = RegisterRISCV::X31;
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pub const FT0: RegisterRISCV = RegisterRISCV::F0;
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pub const FT1: RegisterRISCV = RegisterRISCV::F1;
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pub const FT2: RegisterRISCV = RegisterRISCV::F2;
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pub const FT3: RegisterRISCV = RegisterRISCV::F3;
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pub const FT4: RegisterRISCV = RegisterRISCV::F4;
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pub const FT5: RegisterRISCV = RegisterRISCV::F5;
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pub const FT6: RegisterRISCV = RegisterRISCV::F6;
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pub const FT7: RegisterRISCV = RegisterRISCV::F7;
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pub const FS0: RegisterRISCV = RegisterRISCV::F8;
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pub const FS1: RegisterRISCV = RegisterRISCV::F9;
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pub const FA0: RegisterRISCV = RegisterRISCV::F10;
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pub const FA1: RegisterRISCV = RegisterRISCV::F11;
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pub const FA2: RegisterRISCV = RegisterRISCV::F12;
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pub const FA3: RegisterRISCV = RegisterRISCV::F13;
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pub const FA4: RegisterRISCV = RegisterRISCV::F14;
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pub const FA5: RegisterRISCV = RegisterRISCV::F15;
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pub const FA6: RegisterRISCV = RegisterRISCV::F16;
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pub const FA7: RegisterRISCV = RegisterRISCV::F17;
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pub const FS2: RegisterRISCV = RegisterRISCV::F18;
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pub const FS3: RegisterRISCV = RegisterRISCV::F19;
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pub const FS4: RegisterRISCV = RegisterRISCV::F20;
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pub const FS5: RegisterRISCV = RegisterRISCV::F21;
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pub const FS6: RegisterRISCV = RegisterRISCV::F22;
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pub const FS7: RegisterRISCV = RegisterRISCV::F23;
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pub const FS8: RegisterRISCV = RegisterRISCV::F24;
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pub const FS9: RegisterRISCV = RegisterRISCV::F25;
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pub const FS10: RegisterRISCV = RegisterRISCV::F26;
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pub const FS11: RegisterRISCV = RegisterRISCV::F27;
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pub const FT8: RegisterRISCV = RegisterRISCV::F28;
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pub const FT9: RegisterRISCV = RegisterRISCV::F29;
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pub const FT10: RegisterRISCV = RegisterRISCV::F30;
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pub const FT11: RegisterRISCV = RegisterRISCV::F31;
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}
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impl From<RegisterRISCV> for i32 {
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fn from(r: RegisterRISCV) -> Self {
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r as i32
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}
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}
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