165 lines
4.4 KiB
Forth
165 lines
4.4 KiB
Forth
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
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namespace UnicornManaged.Const
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open System
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[<AutoOpen>]
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module Riscv =
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// RISCV32 CPU
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let UC_CPU_RISCV32_ANY = 0
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let UC_CPU_RISCV32_BASE32 = 1
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let UC_CPU_RISCV32_SIFIVE_E31 = 2
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let UC_CPU_RISCV32_SIFIVE_U34 = 3
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// RISCV64 CPU
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let UC_CPU_RISCV64_ANY = 0
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let UC_CPU_RISCV64_BASE64 = 1
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let UC_CPU_RISCV64_SIFIVE_E51 = 2
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let UC_CPU_RISCV64_SIFIVE_U54 = 3
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// RISCV registers
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let UC_RISCV_REG_INVALID = 0
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// General purpose registers
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let UC_RISCV_REG_X0 = 1
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let UC_RISCV_REG_X1 = 2
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let UC_RISCV_REG_X2 = 3
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let UC_RISCV_REG_X3 = 4
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let UC_RISCV_REG_X4 = 5
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let UC_RISCV_REG_X5 = 6
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let UC_RISCV_REG_X6 = 7
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let UC_RISCV_REG_X7 = 8
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let UC_RISCV_REG_X8 = 9
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let UC_RISCV_REG_X9 = 10
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let UC_RISCV_REG_X10 = 11
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let UC_RISCV_REG_X11 = 12
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let UC_RISCV_REG_X12 = 13
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let UC_RISCV_REG_X13 = 14
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let UC_RISCV_REG_X14 = 15
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let UC_RISCV_REG_X15 = 16
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let UC_RISCV_REG_X16 = 17
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let UC_RISCV_REG_X17 = 18
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let UC_RISCV_REG_X18 = 19
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let UC_RISCV_REG_X19 = 20
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let UC_RISCV_REG_X20 = 21
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let UC_RISCV_REG_X21 = 22
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let UC_RISCV_REG_X22 = 23
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let UC_RISCV_REG_X23 = 24
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let UC_RISCV_REG_X24 = 25
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let UC_RISCV_REG_X25 = 26
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let UC_RISCV_REG_X26 = 27
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let UC_RISCV_REG_X27 = 28
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let UC_RISCV_REG_X28 = 29
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let UC_RISCV_REG_X29 = 30
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let UC_RISCV_REG_X30 = 31
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let UC_RISCV_REG_X31 = 32
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// Floating-point registers
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let UC_RISCV_REG_F0 = 33
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let UC_RISCV_REG_F1 = 34
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let UC_RISCV_REG_F2 = 35
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let UC_RISCV_REG_F3 = 36
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let UC_RISCV_REG_F4 = 37
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let UC_RISCV_REG_F5 = 38
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let UC_RISCV_REG_F6 = 39
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let UC_RISCV_REG_F7 = 40
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let UC_RISCV_REG_F8 = 41
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let UC_RISCV_REG_F9 = 42
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let UC_RISCV_REG_F10 = 43
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let UC_RISCV_REG_F11 = 44
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let UC_RISCV_REG_F12 = 45
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let UC_RISCV_REG_F13 = 46
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let UC_RISCV_REG_F14 = 47
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let UC_RISCV_REG_F15 = 48
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let UC_RISCV_REG_F16 = 49
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let UC_RISCV_REG_F17 = 50
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let UC_RISCV_REG_F18 = 51
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let UC_RISCV_REG_F19 = 52
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let UC_RISCV_REG_F20 = 53
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let UC_RISCV_REG_F21 = 54
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let UC_RISCV_REG_F22 = 55
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let UC_RISCV_REG_F23 = 56
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let UC_RISCV_REG_F24 = 57
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let UC_RISCV_REG_F25 = 58
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let UC_RISCV_REG_F26 = 59
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let UC_RISCV_REG_F27 = 60
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let UC_RISCV_REG_F28 = 61
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let UC_RISCV_REG_F29 = 62
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let UC_RISCV_REG_F30 = 63
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let UC_RISCV_REG_F31 = 64
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let UC_RISCV_REG_PC = 65
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let UC_RISCV_REG_ENDING = 66
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// Alias registers
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let UC_RISCV_REG_ZERO = 1
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let UC_RISCV_REG_RA = 2
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let UC_RISCV_REG_SP = 3
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let UC_RISCV_REG_GP = 4
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let UC_RISCV_REG_TP = 5
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let UC_RISCV_REG_T0 = 6
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let UC_RISCV_REG_T1 = 7
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let UC_RISCV_REG_T2 = 8
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let UC_RISCV_REG_S0 = 9
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let UC_RISCV_REG_FP = 9
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let UC_RISCV_REG_S1 = 10
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let UC_RISCV_REG_A0 = 11
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let UC_RISCV_REG_A1 = 12
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let UC_RISCV_REG_A2 = 13
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let UC_RISCV_REG_A3 = 14
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let UC_RISCV_REG_A4 = 15
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let UC_RISCV_REG_A5 = 16
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let UC_RISCV_REG_A6 = 17
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let UC_RISCV_REG_A7 = 18
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let UC_RISCV_REG_S2 = 19
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let UC_RISCV_REG_S3 = 20
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let UC_RISCV_REG_S4 = 21
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let UC_RISCV_REG_S5 = 22
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let UC_RISCV_REG_S6 = 23
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let UC_RISCV_REG_S7 = 24
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let UC_RISCV_REG_S8 = 25
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let UC_RISCV_REG_S9 = 26
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let UC_RISCV_REG_S10 = 27
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let UC_RISCV_REG_S11 = 28
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let UC_RISCV_REG_T3 = 29
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let UC_RISCV_REG_T4 = 30
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let UC_RISCV_REG_T5 = 31
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let UC_RISCV_REG_T6 = 32
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let UC_RISCV_REG_FT0 = 33
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let UC_RISCV_REG_FT1 = 34
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let UC_RISCV_REG_FT2 = 35
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let UC_RISCV_REG_FT3 = 36
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let UC_RISCV_REG_FT4 = 37
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let UC_RISCV_REG_FT5 = 38
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let UC_RISCV_REG_FT6 = 39
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let UC_RISCV_REG_FT7 = 40
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let UC_RISCV_REG_FS0 = 41
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let UC_RISCV_REG_FS1 = 42
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let UC_RISCV_REG_FA0 = 43
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let UC_RISCV_REG_FA1 = 44
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let UC_RISCV_REG_FA2 = 45
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let UC_RISCV_REG_FA3 = 46
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let UC_RISCV_REG_FA4 = 47
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let UC_RISCV_REG_FA5 = 48
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let UC_RISCV_REG_FA6 = 49
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let UC_RISCV_REG_FA7 = 50
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let UC_RISCV_REG_FS2 = 51
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let UC_RISCV_REG_FS3 = 52
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let UC_RISCV_REG_FS4 = 53
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let UC_RISCV_REG_FS5 = 54
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let UC_RISCV_REG_FS6 = 55
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let UC_RISCV_REG_FS7 = 56
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let UC_RISCV_REG_FS8 = 57
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let UC_RISCV_REG_FS9 = 58
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let UC_RISCV_REG_FS10 = 59
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let UC_RISCV_REG_FS11 = 60
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let UC_RISCV_REG_FT8 = 61
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let UC_RISCV_REG_FT9 = 62
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let UC_RISCV_REG_FT10 = 63
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let UC_RISCV_REG_FT11 = 64
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