200 lines
5.4 KiB
Forth
200 lines
5.4 KiB
Forth
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
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namespace UnicornManaged.Const
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open System
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[<AutoOpen>]
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module Arm =
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// ARM CPU
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let UC_CPU_ARM_926 = 0
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let UC_CPU_ARM_946 = 1
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let UC_CPU_ARM_1026 = 2
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let UC_CPU_ARM_1136_R2 = 3
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let UC_CPU_ARM_1136 = 4
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let UC_CPU_ARM_1176 = 5
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let UC_CPU_ARM_11MPCORE = 6
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let UC_CPU_ARM_CORTEX_M0 = 7
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let UC_CPU_ARM_CORTEX_M3 = 8
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let UC_CPU_ARM_CORTEX_M4 = 9
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let UC_CPU_ARM_CORTEX_M7 = 10
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let UC_CPU_ARM_CORTEX_M33 = 11
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let UC_CPU_ARM_CORTEX_R5 = 12
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let UC_CPU_ARM_CORTEX_R5F = 13
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let UC_CPU_ARM_CORTEX_A7 = 14
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let UC_CPU_ARM_CORTEX_A8 = 15
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let UC_CPU_ARM_CORTEX_A9 = 16
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let UC_CPU_ARM_CORTEX_A15 = 17
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let UC_CPU_ARM_TI925T = 18
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let UC_CPU_ARM_SA1100 = 19
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let UC_CPU_ARM_SA1110 = 20
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let UC_CPU_ARM_PXA250 = 21
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let UC_CPU_ARM_PXA255 = 22
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let UC_CPU_ARM_PXA260 = 23
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let UC_CPU_ARM_PXA261 = 24
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let UC_CPU_ARM_PXA262 = 25
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let UC_CPU_ARM_PXA270 = 26
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let UC_CPU_ARM_PXA270A0 = 27
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let UC_CPU_ARM_PXA270A1 = 28
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let UC_CPU_ARM_PXA270B0 = 29
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let UC_CPU_ARM_PXA270B1 = 30
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let UC_CPU_ARM_PXA270C0 = 31
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let UC_CPU_ARM_PXA270C5 = 32
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let UC_CPU_ARM_MAX = 33
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// ARM registers
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let UC_ARM_REG_INVALID = 0
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let UC_ARM_REG_APSR = 1
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let UC_ARM_REG_APSR_NZCV = 2
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let UC_ARM_REG_CPSR = 3
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let UC_ARM_REG_FPEXC = 4
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let UC_ARM_REG_FPINST = 5
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let UC_ARM_REG_FPSCR = 6
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let UC_ARM_REG_FPSCR_NZCV = 7
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let UC_ARM_REG_FPSID = 8
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let UC_ARM_REG_ITSTATE = 9
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let UC_ARM_REG_LR = 10
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let UC_ARM_REG_PC = 11
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let UC_ARM_REG_SP = 12
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let UC_ARM_REG_SPSR = 13
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let UC_ARM_REG_D0 = 14
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let UC_ARM_REG_D1 = 15
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let UC_ARM_REG_D2 = 16
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let UC_ARM_REG_D3 = 17
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let UC_ARM_REG_D4 = 18
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let UC_ARM_REG_D5 = 19
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let UC_ARM_REG_D6 = 20
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let UC_ARM_REG_D7 = 21
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let UC_ARM_REG_D8 = 22
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let UC_ARM_REG_D9 = 23
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let UC_ARM_REG_D10 = 24
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let UC_ARM_REG_D11 = 25
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let UC_ARM_REG_D12 = 26
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let UC_ARM_REG_D13 = 27
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let UC_ARM_REG_D14 = 28
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let UC_ARM_REG_D15 = 29
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let UC_ARM_REG_D16 = 30
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let UC_ARM_REG_D17 = 31
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let UC_ARM_REG_D18 = 32
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let UC_ARM_REG_D19 = 33
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let UC_ARM_REG_D20 = 34
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let UC_ARM_REG_D21 = 35
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let UC_ARM_REG_D22 = 36
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let UC_ARM_REG_D23 = 37
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let UC_ARM_REG_D24 = 38
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let UC_ARM_REG_D25 = 39
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let UC_ARM_REG_D26 = 40
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let UC_ARM_REG_D27 = 41
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let UC_ARM_REG_D28 = 42
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let UC_ARM_REG_D29 = 43
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let UC_ARM_REG_D30 = 44
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let UC_ARM_REG_D31 = 45
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let UC_ARM_REG_FPINST2 = 46
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let UC_ARM_REG_MVFR0 = 47
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let UC_ARM_REG_MVFR1 = 48
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let UC_ARM_REG_MVFR2 = 49
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let UC_ARM_REG_Q0 = 50
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let UC_ARM_REG_Q1 = 51
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let UC_ARM_REG_Q2 = 52
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let UC_ARM_REG_Q3 = 53
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let UC_ARM_REG_Q4 = 54
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let UC_ARM_REG_Q5 = 55
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let UC_ARM_REG_Q6 = 56
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let UC_ARM_REG_Q7 = 57
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let UC_ARM_REG_Q8 = 58
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let UC_ARM_REG_Q9 = 59
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let UC_ARM_REG_Q10 = 60
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let UC_ARM_REG_Q11 = 61
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let UC_ARM_REG_Q12 = 62
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let UC_ARM_REG_Q13 = 63
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let UC_ARM_REG_Q14 = 64
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let UC_ARM_REG_Q15 = 65
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let UC_ARM_REG_R0 = 66
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let UC_ARM_REG_R1 = 67
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let UC_ARM_REG_R2 = 68
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let UC_ARM_REG_R3 = 69
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let UC_ARM_REG_R4 = 70
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let UC_ARM_REG_R5 = 71
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let UC_ARM_REG_R6 = 72
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let UC_ARM_REG_R7 = 73
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let UC_ARM_REG_R8 = 74
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let UC_ARM_REG_R9 = 75
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let UC_ARM_REG_R10 = 76
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let UC_ARM_REG_R11 = 77
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let UC_ARM_REG_R12 = 78
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let UC_ARM_REG_S0 = 79
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let UC_ARM_REG_S1 = 80
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let UC_ARM_REG_S2 = 81
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let UC_ARM_REG_S3 = 82
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let UC_ARM_REG_S4 = 83
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let UC_ARM_REG_S5 = 84
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let UC_ARM_REG_S6 = 85
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let UC_ARM_REG_S7 = 86
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let UC_ARM_REG_S8 = 87
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let UC_ARM_REG_S9 = 88
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let UC_ARM_REG_S10 = 89
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let UC_ARM_REG_S11 = 90
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let UC_ARM_REG_S12 = 91
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let UC_ARM_REG_S13 = 92
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let UC_ARM_REG_S14 = 93
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let UC_ARM_REG_S15 = 94
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let UC_ARM_REG_S16 = 95
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let UC_ARM_REG_S17 = 96
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let UC_ARM_REG_S18 = 97
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let UC_ARM_REG_S19 = 98
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let UC_ARM_REG_S20 = 99
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let UC_ARM_REG_S21 = 100
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let UC_ARM_REG_S22 = 101
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let UC_ARM_REG_S23 = 102
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let UC_ARM_REG_S24 = 103
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let UC_ARM_REG_S25 = 104
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let UC_ARM_REG_S26 = 105
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let UC_ARM_REG_S27 = 106
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let UC_ARM_REG_S28 = 107
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let UC_ARM_REG_S29 = 108
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let UC_ARM_REG_S30 = 109
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let UC_ARM_REG_S31 = 110
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let UC_ARM_REG_C1_C0_2 = 111
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let UC_ARM_REG_C13_C0_2 = 112
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let UC_ARM_REG_C13_C0_3 = 113
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let UC_ARM_REG_IPSR = 114
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let UC_ARM_REG_MSP = 115
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let UC_ARM_REG_PSP = 116
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let UC_ARM_REG_CONTROL = 117
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let UC_ARM_REG_IAPSR = 118
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let UC_ARM_REG_EAPSR = 119
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let UC_ARM_REG_XPSR = 120
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let UC_ARM_REG_EPSR = 121
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let UC_ARM_REG_IEPSR = 122
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let UC_ARM_REG_PRIMASK = 123
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let UC_ARM_REG_BASEPRI = 124
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let UC_ARM_REG_BASEPRI_MAX = 125
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let UC_ARM_REG_FAULTMASK = 126
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let UC_ARM_REG_APSR_NZCVQ = 127
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let UC_ARM_REG_APSR_G = 128
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let UC_ARM_REG_APSR_NZCVQG = 129
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let UC_ARM_REG_IAPSR_NZCVQ = 130
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let UC_ARM_REG_IAPSR_G = 131
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let UC_ARM_REG_IAPSR_NZCVQG = 132
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let UC_ARM_REG_EAPSR_NZCVQ = 133
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let UC_ARM_REG_EAPSR_G = 134
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let UC_ARM_REG_EAPSR_NZCVQG = 135
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let UC_ARM_REG_XPSR_NZCVQ = 136
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let UC_ARM_REG_XPSR_G = 137
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let UC_ARM_REG_XPSR_NZCVQG = 138
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let UC_ARM_REG_CP_REG = 139
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let UC_ARM_REG_ENDING = 140
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// alias registers
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let UC_ARM_REG_R13 = 12
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let UC_ARM_REG_R14 = 10
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let UC_ARM_REG_R15 = 11
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let UC_ARM_REG_SB = 75
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let UC_ARM_REG_SL = 76
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let UC_ARM_REG_FP = 77
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let UC_ARM_REG_IP = 78
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