602 lines
17 KiB
C
602 lines
17 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
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#include "qemu/typedefs.h"
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#include "unicorn/unicorn.h"
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#include "sysemu/cpus.h"
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#include "sysemu/tcg.h"
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#include "cpu.h"
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#include "uc_priv.h"
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#include "unicorn_common.h"
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#include "unicorn.h"
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ARMCPU *cpu_arm_init(struct uc_struct *uc);
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static void arm_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUARMState *)uc->cpu->env_ptr)->pc = address;
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((CPUARMState *)uc->cpu->env_ptr)->regs[15] = address;
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}
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static void arm_release(void *ctx)
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{
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int i;
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TCGContext *tcg_ctx = (TCGContext *)ctx;
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ARMCPU *cpu = (ARMCPU *)tcg_ctx->uc->cpu;
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CPUTLBDesc *d = cpu->neg.tlb.d;
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CPUTLBDescFast *f = cpu->neg.tlb.f;
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CPUTLBDesc *desc;
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CPUTLBDescFast *fast;
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ARMELChangeHook *entry, *next;
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CPUARMState *env = &cpu->env;
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uint32_t nr;
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release_common(ctx);
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for (i = 0; i < NB_MMU_MODES; i++) {
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desc = &(d[i]);
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fast = &(f[i]);
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g_free(desc->iotlb);
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g_free(fast->table);
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}
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QLIST_FOREACH_SAFE(entry, &cpu->pre_el_change_hooks, node, next)
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{
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QLIST_SAFE_REMOVE(entry, node);
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g_free(entry);
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}
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QLIST_FOREACH_SAFE(entry, &cpu->el_change_hooks, node, next)
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{
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QLIST_SAFE_REMOVE(entry, node);
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g_free(entry);
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}
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if (arm_feature(env, ARM_FEATURE_PMSA) &&
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arm_feature(env, ARM_FEATURE_V7)) {
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nr = cpu->pmsav7_dregion;
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if (nr) {
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if (arm_feature(env, ARM_FEATURE_V8)) {
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g_free(env->pmsav8.rbar[M_REG_NS]);
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g_free(env->pmsav8.rlar[M_REG_NS]);
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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g_free(env->pmsav8.rbar[M_REG_S]);
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g_free(env->pmsav8.rlar[M_REG_S]);
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}
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} else {
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g_free(env->pmsav7.drbar);
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g_free(env->pmsav7.drsr);
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g_free(env->pmsav7.dracr);
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}
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}
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}
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if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
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nr = cpu->sau_sregion;
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if (nr) {
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g_free(env->sau.rbar);
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g_free(env->sau.rlar);
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}
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}
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g_free(cpu->cpreg_indexes);
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g_free(cpu->cpreg_values);
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g_free(cpu->cpreg_vmstate_indexes);
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g_free(cpu->cpreg_vmstate_values);
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g_hash_table_destroy(cpu->cp_regs);
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}
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void arm_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env;
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(void)uc;
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env = uc->cpu->env_ptr;
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memset(env->regs, 0, sizeof(env->regs));
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env->pc = 0;
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}
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/* these functions are implemented in helper.c. */
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#include "exec/helper-head.h"
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uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg);
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void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val);
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static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg)
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{
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uint32_t mask = 0;
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if (reg & 1) {
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mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
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}
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if (!(reg & 4)) {
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mask |= XPSR_NZCV | XPSR_Q; /* APSR */
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if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
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mask |= XPSR_GE;
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}
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}
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if (reg & 2) {
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mask |= (XPSR_IT_0_1 | XPSR_IT_2_7 | XPSR_T); /* EPSR */
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}
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return xpsr_read(env) & mask;
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}
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static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg,
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uint32_t val)
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{
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uint32_t xpsrmask = 0;
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if (reg & 1) {
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xpsrmask |= XPSR_EXCP;
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}
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if (!(reg & 4)) {
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if (mask & 8) {
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xpsrmask |= XPSR_NZCV | XPSR_Q;
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}
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if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
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xpsrmask |= XPSR_GE;
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}
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}
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if (reg & 2) {
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xpsrmask |= (XPSR_IT_0_1 | XPSR_IT_2_7 | XPSR_T);
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}
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xpsr_write(env, val, xpsrmask);
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}
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static uc_err read_cp_reg(CPUARMState *env, uc_arm_cp_reg *cp)
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{
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ARMCPU *cpu = ARM_CPU(env->uc->cpu);
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const ARMCPRegInfo *ri = get_arm_cp_reginfo(
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cpu->cp_regs, ENCODE_CP_REG(cp->cp, cp->is64, cp->sec, cp->crn, cp->crm,
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cp->opc1, cp->opc2));
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if (!ri) {
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return UC_ERR_ARG;
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}
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cp->val = read_raw_cp_reg(env, ri);
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if (!cp->is64) {
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cp->val = cp->val & 0xFFFFFFFF;
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}
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return UC_ERR_OK;
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}
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static uc_err write_cp_reg(CPUARMState *env, uc_arm_cp_reg *cp)
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{
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ARMCPU *cpu = ARM_CPU(env->uc->cpu);
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const ARMCPRegInfo *ri = get_arm_cp_reginfo(
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cpu->cp_regs, ENCODE_CP_REG(cp->cp, cp->is64, cp->sec, cp->crn, cp->crm,
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cp->opc1, cp->opc2));
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if (!ri) {
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return UC_ERR_ARG;
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}
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if (!cp->is64) {
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cp->val = cp->val & 0xFFFFFFFF;
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}
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if (ri->raw_writefn) {
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ri->raw_writefn(env, ri, cp->val);
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} else if (ri->writefn) {
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ri->writefn(env, ri, cp->val);
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} else {
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if (cpreg_field_is_64bit(ri)) {
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CPREG_FIELD64(env, ri) = cp->val;
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} else {
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CPREG_FIELD32(env, ri) = cp->val;
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}
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}
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return UC_ERR_OK;
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}
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static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value)
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{
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uc_err ret = UC_ERR_OK;
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if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12) {
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*(int32_t *)value = env->regs[regid - UC_ARM_REG_R0];
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} else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31) {
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uint32_t reg_index = regid - UC_ARM_REG_D0;
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*(float64 *)value = env->vfp.zregs[reg_index / 2].d[reg_index & 1];
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} else {
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switch (regid) {
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case UC_ARM_REG_APSR:
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if (arm_feature(env, ARM_FEATURE_M)) {
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*(int32_t *)value = v7m_mrs_xpsr(env, 0);
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} else {
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*(int32_t *)value =
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cpsr_read(env) & (CPSR_NZCV | CPSR_Q | CPSR_GE);
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}
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break;
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case UC_ARM_REG_APSR_NZCV:
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*(int32_t *)value = cpsr_read(env) & CPSR_NZCV;
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break;
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case UC_ARM_REG_CPSR:
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*(int32_t *)value = cpsr_read(env);
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break;
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case UC_ARM_REG_SPSR:
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*(int32_t *)value = env->spsr;
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break;
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// case UC_ARM_REG_SP:
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case UC_ARM_REG_R13:
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*(int32_t *)value = env->regs[13];
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break;
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// case UC_ARM_REG_LR:
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case UC_ARM_REG_R14:
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*(int32_t *)value = env->regs[14];
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break;
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// case UC_ARM_REG_PC:
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case UC_ARM_REG_R15:
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*(int32_t *)value = env->regs[15];
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break;
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case UC_ARM_REG_C1_C0_2:
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*(int32_t *)value = env->cp15.cpacr_el1;
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break;
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case UC_ARM_REG_C13_C0_3:
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*(int32_t *)value = env->cp15.tpidrro_el[0];
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break;
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case UC_ARM_REG_FPEXC:
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*(int32_t *)value = env->vfp.xregs[ARM_VFP_FPEXC];
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break;
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case UC_ARM_REG_IPSR:
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*(int32_t *)value = v7m_mrs_xpsr(env, 5);
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break;
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case UC_ARM_REG_MSP:
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*(uint32_t *)value = helper_v7m_mrs(env, 8);
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break;
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case UC_ARM_REG_PSP:
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*(uint32_t *)value = helper_v7m_mrs(env, 9);
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break;
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case UC_ARM_REG_IAPSR:
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*(int32_t *)value = v7m_mrs_xpsr(env, 1);
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break;
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case UC_ARM_REG_EAPSR:
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*(int32_t *)value = v7m_mrs_xpsr(env, 2);
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break;
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case UC_ARM_REG_XPSR:
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*(int32_t *)value = v7m_mrs_xpsr(env, 3);
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break;
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case UC_ARM_REG_EPSR:
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*(int32_t *)value = v7m_mrs_xpsr(env, 6);
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break;
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case UC_ARM_REG_IEPSR:
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*(int32_t *)value = v7m_mrs_xpsr(env, 7);
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break;
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case UC_ARM_REG_PRIMASK:
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*(uint32_t *)value = helper_v7m_mrs(env, 16);
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break;
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case UC_ARM_REG_BASEPRI:
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*(uint32_t *)value = helper_v7m_mrs(env, 17);
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break;
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case UC_ARM_REG_BASEPRI_MAX:
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*(uint32_t *)value = helper_v7m_mrs(env, 18);
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break;
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case UC_ARM_REG_FAULTMASK:
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*(uint32_t *)value = helper_v7m_mrs(env, 19);
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break;
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case UC_ARM_REG_CONTROL:
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*(uint32_t *)value = helper_v7m_mrs(env, 20);
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break;
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case UC_ARM_REG_CP_REG:
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ret = read_cp_reg(env, (uc_arm_cp_reg *)value);
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break;
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}
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}
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return ret;
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}
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static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value)
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{
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uc_err ret = UC_ERR_OK;
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if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12) {
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env->regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
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} else if (regid >= UC_ARM_REG_D0 && regid <= UC_ARM_REG_D31) {
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uint32_t reg_index = regid - UC_ARM_REG_D0;
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env->vfp.zregs[reg_index / 2].d[reg_index & 1] = *(float64 *)value;
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} else {
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switch (regid) {
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case UC_ARM_REG_APSR:
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if (!arm_feature(env, ARM_FEATURE_M)) {
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cpsr_write(env, *(uint32_t *)value,
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(CPSR_NZCV | CPSR_Q | CPSR_GE), CPSRWriteByUnicorn);
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arm_rebuild_hflags(env);
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} else {
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// Same with UC_ARM_REG_APSR_NZCVQ
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v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value);
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}
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break;
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case UC_ARM_REG_APSR_NZCV:
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cpsr_write(env, *(uint32_t *)value, CPSR_NZCV, CPSRWriteByUnicorn);
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arm_rebuild_hflags(env);
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break;
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case UC_ARM_REG_CPSR:
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cpsr_write(env, *(uint32_t *)value, ~0, CPSRWriteByUnicorn);
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arm_rebuild_hflags(env);
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break;
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case UC_ARM_REG_SPSR:
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env->spsr = *(uint32_t *)value;
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break;
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// case UC_ARM_REG_SP:
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case UC_ARM_REG_R13:
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env->regs[13] = *(uint32_t *)value;
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break;
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// case UC_ARM_REG_LR:
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case UC_ARM_REG_R14:
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env->regs[14] = *(uint32_t *)value;
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break;
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// case UC_ARM_REG_PC:
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case UC_ARM_REG_R15:
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env->pc = (*(uint32_t *)value & ~1);
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env->thumb = (*(uint32_t *)value & 1);
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env->uc->thumb = (*(uint32_t *)value & 1);
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env->regs[15] = (*(uint32_t *)value & ~1);
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break;
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// case UC_ARM_REG_C1_C0_2:
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// env->cp15.c1_coproc = *(int32_t *)value;
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// break;
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case UC_ARM_REG_C13_C0_3:
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env->cp15.tpidrro_el[0] = *(int32_t *)value;
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break;
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case UC_ARM_REG_FPEXC:
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env->vfp.xregs[ARM_VFP_FPEXC] = *(int32_t *)value;
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break;
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case UC_ARM_REG_IPSR:
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v7m_msr_xpsr(env, 0b1000, 5, *(uint32_t *)value);
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break;
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case UC_ARM_REG_MSP:
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helper_v7m_msr(env, 8, *(uint32_t *)value);
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break;
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case UC_ARM_REG_PSP:
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helper_v7m_msr(env, 9, *(uint32_t *)value);
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break;
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case UC_ARM_REG_CONTROL:
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helper_v7m_msr(env, 20, *(uint32_t *)value);
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break;
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case UC_ARM_REG_EPSR:
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v7m_msr_xpsr(env, 0b1000, 6, *(uint32_t *)value);
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break;
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case UC_ARM_REG_IEPSR:
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v7m_msr_xpsr(env, 0b1000, 7, *(uint32_t *)value);
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break;
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case UC_ARM_REG_PRIMASK:
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helper_v7m_msr(env, 16, *(uint32_t *)value);
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break;
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case UC_ARM_REG_BASEPRI:
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helper_v7m_msr(env, 17, *(uint32_t *)value);
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break;
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case UC_ARM_REG_BASEPRI_MAX:
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helper_v7m_msr(env, 18, *(uint32_t *)value);
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break;
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case UC_ARM_REG_FAULTMASK:
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helper_v7m_msr(env, 19, *(uint32_t *)value);
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break;
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case UC_ARM_REG_APSR_NZCVQ:
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v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value);
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break;
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case UC_ARM_REG_APSR_G:
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v7m_msr_xpsr(env, 0b0100, 0, *(uint32_t *)value);
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break;
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case UC_ARM_REG_APSR_NZCVQG:
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v7m_msr_xpsr(env, 0b1100, 0, *(uint32_t *)value);
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break;
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case UC_ARM_REG_IAPSR:
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case UC_ARM_REG_IAPSR_NZCVQ:
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v7m_msr_xpsr(env, 0b1000, 1, *(uint32_t *)value);
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break;
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case UC_ARM_REG_IAPSR_G:
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v7m_msr_xpsr(env, 0b0100, 1, *(uint32_t *)value);
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break;
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case UC_ARM_REG_IAPSR_NZCVQG:
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v7m_msr_xpsr(env, 0b1100, 1, *(uint32_t *)value);
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break;
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case UC_ARM_REG_EAPSR:
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case UC_ARM_REG_EAPSR_NZCVQ:
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v7m_msr_xpsr(env, 0b1000, 2, *(uint32_t *)value);
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break;
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case UC_ARM_REG_EAPSR_G:
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v7m_msr_xpsr(env, 0b0100, 2, *(uint32_t *)value);
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break;
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case UC_ARM_REG_EAPSR_NZCVQG:
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v7m_msr_xpsr(env, 0b1100, 2, *(uint32_t *)value);
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break;
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case UC_ARM_REG_XPSR:
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case UC_ARM_REG_XPSR_NZCVQ:
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v7m_msr_xpsr(env, 0b1000, 3, *(uint32_t *)value);
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break;
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case UC_ARM_REG_XPSR_G:
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v7m_msr_xpsr(env, 0b0100, 3, *(uint32_t *)value);
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break;
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case UC_ARM_REG_XPSR_NZCVQG:
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v7m_msr_xpsr(env, 0b1100, 3, *(uint32_t *)value);
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break;
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case UC_ARM_REG_CP_REG:
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ret = write_cp_reg(env, (uc_arm_cp_reg *)value);
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break;
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}
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}
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return ret;
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}
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int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals,
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int count)
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{
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CPUARMState *env = &(ARM_CPU(uc->cpu)->env);
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int i;
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uc_err err;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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err = reg_read(env, regid, value);
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if (err) {
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return err;
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}
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}
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return 0;
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}
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int arm_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
|
|
int count)
|
|
{
|
|
CPUArchState *env = &(ARM_CPU(uc->cpu)->env);
|
|
int i;
|
|
uc_err err;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
unsigned int regid = regs[i];
|
|
const void *value = vals[i];
|
|
err = reg_write(env, regid, value);
|
|
if (err) {
|
|
return err;
|
|
}
|
|
if (regid == UC_ARM_REG_R15) {
|
|
// force to quit execution and flush TB
|
|
uc->quit_request = true;
|
|
uc_emu_stop(uc);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFAULT_VISIBILITY
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
int armeb_context_reg_read(struct uc_context *ctx, unsigned int *regs,
|
|
void **vals, int count)
|
|
#else
|
|
int arm_context_reg_read(struct uc_context *ctx, unsigned int *regs,
|
|
void **vals, int count)
|
|
#endif
|
|
{
|
|
CPUARMState *env = (CPUARMState *)ctx->data;
|
|
int i;
|
|
uc_err err;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
unsigned int regid = regs[i];
|
|
void *value = vals[i];
|
|
err = reg_read(env, regid, value);
|
|
if (err) {
|
|
return err;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFAULT_VISIBILITY
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
int armeb_context_reg_write(struct uc_context *ctx, unsigned int *regs,
|
|
void *const *vals, int count)
|
|
#else
|
|
int arm_context_reg_write(struct uc_context *ctx, unsigned int *regs,
|
|
void *const *vals, int count)
|
|
#endif
|
|
{
|
|
CPUARMState *env = (CPUARMState *)ctx->data;
|
|
int i;
|
|
uc_err err;
|
|
|
|
for (i = 0; i < count; i++) {
|
|
unsigned int regid = regs[i];
|
|
const void *value = vals[i];
|
|
err = reg_write(env, regid, value);
|
|
if (err) {
|
|
return err;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool arm_stop_interrupt(struct uc_struct *uc, int intno)
|
|
{
|
|
switch (intno) {
|
|
default:
|
|
return false;
|
|
case EXCP_UDEF:
|
|
case EXCP_YIELD:
|
|
return true;
|
|
case EXCP_INVSTATE:
|
|
uc->invalid_error = UC_ERR_EXCEPTION;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
static uc_err arm_query(struct uc_struct *uc, uc_query_type type,
|
|
size_t *result)
|
|
{
|
|
CPUState *mycpu = uc->cpu;
|
|
uint32_t mode;
|
|
|
|
switch (type) {
|
|
case UC_QUERY_MODE:
|
|
// zero out ARM/THUMB mode
|
|
mode = uc->mode & ~(UC_MODE_ARM | UC_MODE_THUMB);
|
|
// THUMB mode or ARM MOde
|
|
mode |=
|
|
((ARM_CPU(mycpu)->env.thumb != 0) ? UC_MODE_THUMB : UC_MODE_ARM);
|
|
*result = mode;
|
|
return UC_ERR_OK;
|
|
default:
|
|
return UC_ERR_ARG;
|
|
}
|
|
}
|
|
|
|
static bool arm_opcode_hook_invalidate(uint32_t op, uint32_t flags)
|
|
{
|
|
if (op != UC_TCG_OP_SUB) {
|
|
return false;
|
|
}
|
|
|
|
if (flags == UC_TCG_OP_FLAG_CMP && op != UC_TCG_OP_SUB) {
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static int arm_cpus_init(struct uc_struct *uc, const char *cpu_model)
|
|
{
|
|
ARMCPU *cpu;
|
|
|
|
cpu = cpu_arm_init(uc);
|
|
if (cpu == NULL) {
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
void armeb_uc_init(struct uc_struct *uc)
|
|
#else
|
|
void arm_uc_init(struct uc_struct *uc)
|
|
#endif
|
|
{
|
|
uc->reg_read = arm_reg_read;
|
|
uc->reg_write = arm_reg_write;
|
|
uc->reg_reset = arm_reg_reset;
|
|
uc->set_pc = arm_set_pc;
|
|
uc->stop_interrupt = arm_stop_interrupt;
|
|
uc->release = arm_release;
|
|
uc->query = arm_query;
|
|
uc->cpus_init = arm_cpus_init;
|
|
uc->opcode_hook_invalidate = arm_opcode_hook_invalidate;
|
|
uc->cpu_context_size = offsetof(CPUARMState, cpu_watchpoint);
|
|
uc_common_init(uc);
|
|
}
|