uc_ctl proposal (#1473)
* Add uc_ctl * Add comments * Slightly changed for bindings generation * Generate bindings
This commit is contained in:
@ -1,5 +1,15 @@
|
||||
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
|
||||
|
||||
UC_CPU_RISCV32_ANY = 0
|
||||
UC_CPU_RISCV32_BASE32 = 1
|
||||
UC_CPU_RISCV32_SIFIVE_E31 = 2
|
||||
UC_CPU_RISCV32_SIFIVE_U34 = 3
|
||||
|
||||
UC_CPU_RISCV64_ANY = 0
|
||||
UC_CPU_RISCV64_BASE64 = 1
|
||||
UC_CPU_RISCV64_SIFIVE_E51 = 2
|
||||
UC_CPU_RISCV64_SIFIVE_U54 = 3
|
||||
|
||||
# RISCV registers
|
||||
|
||||
UC_RISCV_REG_INVALID = 0
|
||||
|
Reference in New Issue
Block a user