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uc_ctl proposal (#1473)

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* Add uc_ctl

* Add comments

* Slightly changed for bindings generation

* Generate bindings
This commit is contained in:
lazymio
2021-10-30 04:45:32 +02:00
committed by GitHub
parent 1856e940e4
commit 090686f8ed
65 changed files with 3520 additions and 4 deletions
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36
include/unicorn/arm.h
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@ -15,6 +15,42 @@ extern "C" {
#pragma warning(disable : 4201)
#endif
typedef enum uc_cpu_arm {
UC_CPU_ARM_926 = 0,
UC_CPU_ARM_946,
UC_CPU_ARM_1026,
UC_CPU_ARM_1136_R2,
UC_CPU_ARM_1136,
UC_CPU_ARM_1176,
UC_CPU_ARM_11MPCORE,
UC_CPU_ARM_CORTEX_M0,
UC_CPU_ARM_CORTEX_M3,
UC_CPU_ARM_CORTEX_M4,
UC_CPU_ARM_CORTEX_M7,
UC_CPU_ARM_CORTEX_M33,
UC_CPU_ARM_CORTEX_R5,
UC_CPU_ARM_CORTEX_R5F,
UC_CPU_ARM_CORTEX_A8,
UC_CPU_ARM_CORTEX_A9,
UC_CPU_ARM_CORTEX_A7,
UC_CPU_ARM_CORTEX_A15,
UC_CPU_ARM_TI925T,
UC_CPU_ARM_SA1100,
UC_CPU_ARM_SA1110,
UC_CPU_ARM_PXA250,
UC_CPU_ARM_PXA255,
UC_CPU_ARM_PXA260,
UC_CPU_ARM_PXA261,
UC_CPU_ARM_PXA262,
UC_CPU_ARM_PXA270A0,
UC_CPU_ARM_PXA270A1,
UC_CPU_ARM_PXA270B0,
UC_CPU_ARM_PXA270B1,
UC_CPU_ARM_PXA270C0,
UC_CPU_ARM_PXA270C5,
UC_CPU_ARM_MAX
} uc_cpu_arm;
//> ARM registers
typedef enum uc_arm_reg {
UC_ARM_REG_INVALID = 0,

7
include/unicorn/arm64.h
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@ -15,6 +15,13 @@ extern "C" {
#pragma warning(disable : 4201)
#endif
typedef enum uc_cpu_aarch64 {
UC_CPU_AARCH64_A57 = 0,
UC_CPU_AARCH64_A53,
UC_CPU_AARCH64_A72,
UC_CPU_AARCH64_MAX
} uc_cpu_aarch64;
//> ARM64 registers
typedef enum uc_arm64_reg {
UC_ARM64_REG_INVALID = 0,

12
include/unicorn/m68k.h
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@ -15,6 +15,18 @@ extern "C" {
#pragma warning(disable : 4201)
#endif
typedef enum uc_cpu_m68k {
UC_CPU_M5206_CPU = 0,
UC_CPU_M68000_CPU,
UC_CPU_M68020_CPU,
UC_CPU_M68030_CPU,
UC_CPU_M68040_CPU,
UC_CPU_M68060_CPU,
UC_CPU_M5208_CPU,
UC_CPU_CFV4E_CPU,
UC_CPU_ANY_CPU,
} uc_cpu_m68k;
//> M68K registers
typedef enum uc_m68k_reg {
UC_M68K_REG_INVALID = 0,

32
include/unicorn/mips.h
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@ -19,6 +19,38 @@ extern "C" {
#pragma warning(disable : 4201)
#endif
typedef enum uc_cpu_mips {
UC_CPU_MIPS_4KC = 0,
UC_CPU_MIPS_4KM,
UC_CPU_MIPS_4KECR1,
UC_CPU_MIPS_4KEMR1,
UC_CPU_MIPS_4KEC,
UC_CPU_MIPS_4KEM,
UC_CPU_MIPS_24KC,
UC_CPU_MIPS_24KEC,
UC_CPU_MIPS_24KF,
UC_CPU_MIPS_34KF,
UC_CPU_MIPS_74KF,
UC_CPU_MIPS_M14K,
UC_CPU_MIPS_M14KC,
UC_CPU_MIPS_P5600,
UC_CPU_MIPS_MIPS32R6_GENERIC,
UC_CPU_MIPS_I7200,
UC_CPU_MIPS_R4000,
UC_CPU_MIPS_VR5432,
UC_CPU_MIPS_5KC,
UC_CPU_MIPS_5KF,
UC_CPU_MIPS_20KC,
UC_CPU_MIPS_MIPS64R2_GENERIC,
UC_CPU_MIPS_5KEC,
UC_CPU_MIPS_5KEF,
UC_CPU_MIPS_I6400,
UC_CPU_MIPS_I6500,
UC_CPU_MIPS_LOONGSON_2E,
UC_CPU_MIPS_LOONGSON_2F,
UC_CPU_MIPS_MIPS64DSPR2
} uc_cpu_mips;
//> MIPS registers
typedef enum UC_MIPS_REG {
UC_MIPS_REG_INVALID = 0,

305
include/unicorn/ppc.h
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@ -15,6 +15,311 @@ extern "C" {
#pragma warning(disable : 4201)
#endif
typedef enum uc_cpu_ppc {
UC_CPU_PPC_401A1 = 0,
UC_CPU_PPC_401B2,
UC_CPU_PPC_401C2,
UC_CPU_PPC_401D2,
UC_CPU_PPC_401E2,
UC_CPU_PPC_401F2,
UC_CPU_PPC_401G2,
UC_CPU_PPC_COBRA,
UC_CPU_PPC_403GA,
UC_CPU_PPC_403GB,
UC_CPU_PPC_403GC,
UC_CPU_PPC_403GCX,
UC_CPU_PPC_405D2,
UC_CPU_PPC_405D4,
UC_CPU_PPC_405CRA,
UC_CPU_PPC_405CRB,
UC_CPU_PPC_405CRC,
UC_CPU_PPC_405EP,
UC_CPU_PPC_405EZ,
UC_CPU_PPC_405GPA,
UC_CPU_PPC_405GPB,
UC_CPU_PPC_405GPC,
UC_CPU_PPC_405GPD,
UC_CPU_PPC_405GPR,
UC_CPU_PPC_405LP,
UC_CPU_PPC_NPE405H,
UC_CPU_PPC_NPE405H2,
UC_CPU_PPC_NPE405L,
UC_CPU_PPC_NPE4GS3,
UC_CPU_PPC_STB03,
UC_CPU_PPC_STB04,
UC_CPU_PPC_STB25,
UC_CPU_PPC_X2VP4,
UC_CPU_PPC_440_XILINX,
UC_CPU_PPC_440EPA,
UC_CPU_PPC_440EPB,
UC_CPU_PPC_440GPB,
UC_CPU_PPC_440GPC,
UC_CPU_PPC_440GRX,
UC_CPU_PPC_440GXA,
UC_CPU_PPC_440GXB,
UC_CPU_PPC_440GXC,
UC_CPU_PPC_440GXF,
UC_CPU_PPC_440SP,
UC_CPU_PPC_440SP2,
UC_CPU_PPC_440SPE,
UC_CPU_PPC_460EXB,
UC_CPU_PPC_MPC5XX,
UC_CPU_PPC_MPC8XX,
UC_CPU_PPC_G2,
UC_CPU_PPC_G2H4,
UC_CPU_PPC_G2GP,
UC_CPU_PPC_G2LS,
UC_CPU_PPC_MPC603,
UC_CPU_PPC_G2_HIP3,
UC_CPU_PPC_G2_HIP4,
UC_CPU_PPC_G2LE,
UC_CPU_PPC_G2LEGP,
UC_CPU_PPC_G2LELS,
UC_CPU_PPC_G2LEGP1,
UC_CPU_PPC_G2LEGP3,
UC_CPU_PPC_E200Z5,
UC_CPU_PPC_E200Z6,
UC_CPU_PPC_E300C1,
UC_CPU_PPC_E300C2,
UC_CPU_PPC_E300C3,
UC_CPU_PPC_E300C4,
UC_CPU_PPC_E500V1_V10,
UC_CPU_PPC_E500V1_V20,
UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_E500V2_V11,
UC_CPU_PPC_E500V2_V20,
UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_E500V2_V30,
UC_CPU_PPC_E500MC,
UC_CPU_PPC_E5500,
UC_CPU_PPC_E6500,
UC_CPU_PPC_E600,
UC_CPU_PPC_601_V0,
UC_CPU_PPC_601_V1,
UC_CPU_PPC_601_V2,
UC_CPU_PPC_602,
UC_CPU_PPC_603,
UC_CPU_PPC_603E_V11,
UC_CPU_PPC_603E_V12,
UC_CPU_PPC_603E_V13,
UC_CPU_PPC_603E_V14,
UC_CPU_PPC_603E_V22,
UC_CPU_PPC_603E_V3,
UC_CPU_PPC_603E_V4,
UC_CPU_PPC_603E_V41,
UC_CPU_PPC_603E7T,
UC_CPU_PPC_603E7V,
UC_CPU_PPC_603E7V1,
UC_CPU_PPC_603E7V2,
UC_CPU_PPC_603E7,
UC_CPU_PPC_603P,
UC_CPU_PPC_604,
UC_CPU_PPC_604E_V10,
UC_CPU_PPC_604E_V22,
UC_CPU_PPC_604E_V24,
UC_CPU_PPC_604R,
UC_CPU_PPC_7X0_V10,
UC_CPU_PPC_7X0_V20,
UC_CPU_PPC_7X0_V21,
UC_CPU_PPC_7X0_V22,
UC_CPU_PPC_7X0_V30,
UC_CPU_PPC_7X0_V31,
UC_CPU_PPC_740E,
UC_CPU_PPC_750E,
UC_CPU_PPC_7X0P,
UC_CPU_PPC_750CL_V10,
UC_CPU_PPC_750CL_V20,
UC_CPU_PPC_750CX_V10,
UC_CPU_PPC_750CX_V20,
UC_CPU_PPC_750CX_V21,
UC_CPU_PPC_750CX_V22,
UC_CPU_PPC_750CXE_V21,
UC_CPU_PPC_750CXE_V22,
UC_CPU_PPC_750CXE_V23,
UC_CPU_PPC_750CXE_V24,
UC_CPU_PPC_750CXE_V24B,
UC_CPU_PPC_750CXE_V30,
UC_CPU_PPC_750CXE_V31,
UC_CPU_PPC_750CXE_V31B,
UC_CPU_PPC_750CXR,
UC_CPU_PPC_750FL,
UC_CPU_PPC_750FX_V10,
UC_CPU_PPC_750FX_V20,
UC_CPU_PPC_750FX_V21,
UC_CPU_PPC_750FX_V22,
UC_CPU_PPC_750FX_V23,
UC_CPU_PPC_750GL,
UC_CPU_PPC_750GX_V10,
UC_CPU_PPC_750GX_V11,
UC_CPU_PPC_750GX_V12,
UC_CPU_PPC_750L_V20,
UC_CPU_PPC_750L_V21,
UC_CPU_PPC_750L_V22,
UC_CPU_PPC_750L_V30,
UC_CPU_PPC_750L_V32,
UC_CPU_PPC_7X5_V10,
UC_CPU_PPC_7X5_V11,
UC_CPU_PPC_7X5_V20,
UC_CPU_PPC_7X5_V21,
UC_CPU_PPC_7X5_V22,
UC_CPU_PPC_7X5_V23,
UC_CPU_PPC_7X5_V24,
UC_CPU_PPC_7X5_V25,
UC_CPU_PPC_7X5_V26,
UC_CPU_PPC_7X5_V27,
UC_CPU_PPC_7X5_V28,
UC_CPU_PPC_7400_V10,
UC_CPU_PPC_7400_V11,
UC_CPU_PPC_7400_V20,
UC_CPU_PPC_7400_V21,
UC_CPU_PPC_7400_V22,
UC_CPU_PPC_7400_V26,
UC_CPU_PPC_7400_V27,
UC_CPU_PPC_7400_V28,
UC_CPU_PPC_7400_V29,
UC_CPU_PPC_7410_V10,
UC_CPU_PPC_7410_V11,
UC_CPU_PPC_7410_V12,
UC_CPU_PPC_7410_V13,
UC_CPU_PPC_7410_V14,
UC_CPU_PPC_7448_V10,
UC_CPU_PPC_7448_V11,
UC_CPU_PPC_7448_V20,
UC_CPU_PPC_7448_V21,
UC_CPU_PPC_7450_V10,
UC_CPU_PPC_7450_V11,
UC_CPU_PPC_7450_V12,
UC_CPU_PPC_7450_V20,
UC_CPU_PPC_7450_V21,
UC_CPU_PPC_74X1_V23,
UC_CPU_PPC_74X1_V210,
UC_CPU_PPC_74X5_V10,
UC_CPU_PPC_74X5_V21,
UC_CPU_PPC_74X5_V32,
UC_CPU_PPC_74X5_V33,
UC_CPU_PPC_74X5_V34,
UC_CPU_PPC_74X7_V10,
UC_CPU_PPC_74X7_V11,
UC_CPU_PPC_74X7_V12,
UC_CPU_PPC_74X7A_V10,
UC_CPU_PPC_74X7A_V11,
UC_CPU_PPC_74X7A_V12,
UC_CPU_PPC_IOP480 = UC_CPU_PPC_401B2,
UC_CPU_PPC_X2VP20 = UC_CPU_PPC_440GXF,
UC_CPU_PPC_440GRA = UC_CPU_PPC_440EPB,
UC_CPU_PPC_440EPX = UC_CPU_PPC_440GRX,
UC_CPU_PPC_MPC5200_V10 = UC_CPU_PPC_G2LEGP1,
UC_CPU_PPC_MPC5200_V11 = UC_CPU_PPC_G2LEGP1,
UC_CPU_PPC_MPC5200_V12 = UC_CPU_PPC_G2LEGP1,
UC_CPU_PPC_MPC5200B_V20 = UC_CPU_PPC_G2LEGP1,
UC_CPU_PPC_MPC5200B_V21 = UC_CPU_PPC_G2LEGP1,
UC_CPU_PPC_MPC834X = UC_CPU_PPC_E300C1,
UC_CPU_PPC_MPC837X = UC_CPU_PPC_E300C4,
UC_CPU_PPC_E500 = UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_MPC8533_V10 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8533_V11 = UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_MPC8533E_V10 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8533E_V11 = UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_MPC8540_V10 = UC_CPU_PPC_E500V1_V10,
UC_CPU_PPC_MPC8540_V20 = UC_CPU_PPC_E500V1_V20,
UC_CPU_PPC_MPC8540_V21 = UC_CPU_PPC_E500V1_V20,
UC_CPU_PPC_MPC8541_V10 = UC_CPU_PPC_E500V1_V20,
UC_CPU_PPC_MPC8541_V11 = UC_CPU_PPC_E500V1_V20,
UC_CPU_PPC_MPC8541E_V10 = UC_CPU_PPC_E500V1_V20,
UC_CPU_PPC_MPC8541E_V11 = UC_CPU_PPC_E500V1_V20,
UC_CPU_PPC_MPC8543_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8543_V11 = UC_CPU_PPC_E500V2_V11,
UC_CPU_PPC_MPC8543_V20 = UC_CPU_PPC_E500V2_V20,
UC_CPU_PPC_MPC8543_V21 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8543E_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8543E_V11 = UC_CPU_PPC_E500V2_V11,
UC_CPU_PPC_MPC8543E_V20 = UC_CPU_PPC_E500V2_V20,
UC_CPU_PPC_MPC8543E_V21 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8544_V10 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8544_V11 = UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_MPC8544E_V11 = UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_MPC8544E_V10 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8545_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8545_V20 = UC_CPU_PPC_E500V2_V20,
UC_CPU_PPC_MPC8545_V21 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8545E_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8545E_V20 = UC_CPU_PPC_E500V2_V20,
UC_CPU_PPC_MPC8545E_V21 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8547E_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8547E_V20 = UC_CPU_PPC_E500V2_V20,
UC_CPU_PPC_MPC8547E_V21 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8548_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8548_V11 = UC_CPU_PPC_E500V2_V11,
UC_CPU_PPC_MPC8548_V20 = UC_CPU_PPC_E500V2_V20,
UC_CPU_PPC_MPC8548_V21 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8548E_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8548E_V11 = UC_CPU_PPC_E500V2_V11,
UC_CPU_PPC_MPC8548E_V20 = UC_CPU_PPC_E500V2_V20,
UC_CPU_PPC_MPC8548E_V21 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8555_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8555_V11 = UC_CPU_PPC_E500V2_V11,
UC_CPU_PPC_MPC8555E_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8555E_V11 = UC_CPU_PPC_E500V2_V11,
UC_CPU_PPC_MPC8560_V10 = UC_CPU_PPC_E500V2_V10,
UC_CPU_PPC_MPC8560_V20 = UC_CPU_PPC_E500V2_V20,
UC_CPU_PPC_MPC8560_V21 = UC_CPU_PPC_E500V2_V21,
UC_CPU_PPC_MPC8567 = UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_MPC8567E = UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_MPC8568 = UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_MPC8568E = UC_CPU_PPC_E500V2_V22,
UC_CPU_PPC_MPC8572 = UC_CPU_PPC_E500V2_V30,
UC_CPU_PPC_MPC8572E = UC_CPU_PPC_E500V2_V30,
UC_CPU_PPC_MPC8610 = UC_CPU_PPC_E600,
UC_CPU_PPC_MPC8641 = UC_CPU_PPC_E600,
UC_CPU_PPC_MPC8641D = UC_CPU_PPC_E600,
} uc_cpu_ppc;
typedef enum uc_cpu_ppc64 {
UC_CPU_PPC64_620 = 0,
UC_CPU_PPC64_630,
UC_CPU_PPC64_631,
UC_CPU_PPC64_POWER4,
UC_CPU_PPC64_POWER4P,
UC_CPU_PPC64_POWER5,
UC_CPU_PPC64_POWER5P_V21,
UC_CPU_PPC64_POWER6,
UC_CPU_PPC64_POWER_SERVER_MASK,
UC_CPU_PPC64_POWER7_BASE,
UC_CPU_PPC64_POWER7_V23,
UC_CPU_PPC64_POWER7P_BASE,
UC_CPU_PPC64_POWER7P_V21,
UC_CPU_PPC64_POWER8E_BASE,
UC_CPU_PPC64_POWER8E_V21,
UC_CPU_PPC64_POWER8_BASE,
UC_CPU_PPC64_POWER8_V20,
UC_CPU_PPC64_POWER8NVL_BASE,
UC_CPU_PPC64_POWER8NVL_V10,
UC_CPU_PPC64_POWER9_BASE,
UC_CPU_PPC64_POWER9_DD1,
UC_CPU_PPC64_POWER9_DD20,
UC_CPU_PPC64_POWER10_BASE,
UC_CPU_PPC64_POWER10_DD1,
UC_CPU_PPC64_970_V22,
UC_CPU_PPC64_970FX_V10,
UC_CPU_PPC64_970FX_V20,
UC_CPU_PPC64_970FX_V21,
UC_CPU_PPC64_970FX_V30,
UC_CPU_PPC64_970FX_V31,
UC_CPU_PPC64_970MP_V10,
UC_CPU_PPC64_970MP_V11,
UC_CPU_PPC64_CELL_V10,
UC_CPU_PPC64_CELL_V20,
UC_CPU_PPC64_CELL_V30,
UC_CPU_PPC64_CELL_V31,
UC_CPU_PPC64_RS64,
UC_CPU_PPC64_RS64II,
UC_CPU_PPC64_RS64III,
UC_CPU_PPC64_RS64IV,
UC_CPU_PPC64_CELL_V32 = UC_CPU_PPC64_CELL_V31,
UC_CPU_PPC64_CELL = UC_CPU_PPC64_CELL_V32,
} uc_cpu_ppc64;
//> PPC registers
typedef enum uc_ppc_reg {
UC_PPC_REG_INVALID = 0,

14
include/unicorn/riscv.h
View File

@ -15,6 +15,20 @@ extern "C" {
#pragma warning(disable : 4201)
#endif
typedef enum uc_cpu_riscv32 {
UC_CPU_RISCV32_ANY = 0,
UC_CPU_RISCV32_BASE32,
UC_CPU_RISCV32_SIFIVE_E31,
UC_CPU_RISCV32_SIFIVE_U34,
} uc_cpu_riscv32;
typedef enum uc_cpu_riscv64 {
UC_CPU_RISCV64_ANY = 0,
UC_CPU_RISCV64_BASE64,
UC_CPU_RISCV64_SIFIVE_E51,
UC_CPU_RISCV64_SIFIVE_U54,
} uc_cpu_riscv64;
//> RISCV registers
typedef enum uc_riscv_reg {
UC_RISCV_REG_INVALID = 0,

36
include/unicorn/sparc.h
View File

@ -19,6 +19,42 @@ extern "C" {
#pragma warning(disable : 4201)
#endif
typedef enum uc_cpu_sparc {
UC_CPU_SPARC_FUJITSU_MB86904 = 0,
UC_CPU_SPARC_FUJITSU_MB86907,
UC_CPU_SPARC_TI_MICROSPARC_I,
UC_CPU_SPARC_TI_MICROSPARC_II,
UC_CPU_SPARC_TI_MICROSPARC_IIEP,
UC_CPU_SPARC_TI_SUPERSPARC_40,
UC_CPU_SPARC_TI_SUPERSPARC_50,
UC_CPU_SPARC_TI_SUPERSPARC_51,
UC_CPU_SPARC_TI_SUPERSPARC_60,
UC_CPU_SPARC_TI_SUPERSPARC_61,
UC_CPU_SPARC_TI_SUPERSPARC_II,
UC_CPU_SPARC_LEON2,
UC_CPU_SPARC_LEON3
} uc_cpu_sparc;
typedef enum uc_cpu_sparc64 {
UC_CPU_SPARC64_FUJITSU = 0,
UC_CPU_SPARC64_FUJITSU_III,
UC_CPU_SPARC64_FUJITSU_IV,
UC_CPU_SPARC64_FUJITSU_V,
UC_CPU_SPARC64_TI_ULTRASPARC_I,
UC_CPU_SPARC64_TI_ULTRASPARC_II,
UC_CPU_SPARC64_TI_ULTRASPARC_III,
UC_CPU_SPARC64_TI_ULTRASPARC_IIE,
UC_CPU_SPARC64_SUN_ULTRASPARC_III,
UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU,
UC_CPU_SPARC64_SUN_ULTRASPARC_IIII,
UC_CPU_SPARC64_SUN_ULTRASPARC_IV,
UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS,
UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS,
UC_CPU_SPARC64_SUN_ULTRASPARC_T1,
UC_CPU_SPARC64_SUN_ULTRASPARC_T2,
UC_CPU_SPARC64_NEC_ULTRASPARC_I,
} uc_cpu_sparc64;
//> SPARC registers
typedef enum uc_sparc_reg {
UC_SPARC_REG_INVALID = 0,

116
include/unicorn/unicorn.h
View File

@ -391,6 +391,108 @@ typedef enum uc_query_type {
// result = True)
} uc_query_type;
// The implementation of uc_ctl is like what Linux ioctl does but slightly
// different.
//
// A uc_control_type passed to uc_ctl is constructed as:
//
// R/W NR Reserved Type
// [ ] [ ] [ ] [ ]
// 31 30 29 26 25 16 15 0
//
// @R/W: Whether the operation is a read or write access.
// @NR: Number of arguments.
// @Reserved: Should be zero, reserved for future extension.
// @Type: Taken from uc_control_type enum.
//
// See the helper macros below.
// No input and output arguments.
#define UC_CTL_IO_NONE (0)
// The arguments are used for input.
#define UC_CTL_IO_WRITE (1)
// The arguments are used for ouput.
#define UC_CTL_IO_READ (2)
// The arguments include both input and output arugments.
#define UC_CTL_IO_READ_WRITE (UC_CTL_IO_WRITE | UC_CTL_IO_READ)
#define UC_CTL(type, nr, rw) ((type) | ((nr) << 26) | ((rw) << 30))
#define UC_CTL_NONE(type, nr) UC_CTL(type, nr, UC_CTL_IO_NONE)
#define UC_CTL_READ(type, nr) UC_CTL(type, nr, UC_CTL_IO_READ)
#define UC_CTL_WRITE(type, nr) UC_CTL(type, nr, UC_CTL_IO_WRITE)
#define UC_CTL_READ_WRITE(type, nr) UC_CTL(type, nr, UC_CTL_IO_READ_WRITE)
// All type of controls for uc_ctl API.
// The controls are organized in a tree level.
// If a control don't have `Set` or `Get` for @args, it means it's r/o or w/o.
typedef enum uc_control_type {
// Current mode.
// Read: @args = (*int)
UC_CTL_UC_MODE = 0,
// Curent page size.
// Write: @args = (int)
// Read: @args = (*int)
UC_CTL_UC_PAGE_SIZE,
// Current arch.
// Read: @args = (*int)
UC_CTL_UC_ARCH,
// Current timeout.
// Read: @args = (*uint64_t)
UC_CTL_UC_TIMEOUT,
// The number of current exists.
// Read: @args = (*size_t)
UC_CTL_UC_EXITS_CNT,
// Current exists.
// Write: @args = (*uint64_t exists, size_t len)
// @len = UC_CTL_UC_EXITS_CNT
// Read: @args = (*uint64_t exists, size_t len)
// @len = UC_CTL_UC_EXITS_CNT
UC_CTL_UC_EXITS,
// Set the cpu model of uc.
// Note this option can only be set before any Unicorn
// API is called except for uc_open.
// Write: @args = (int)
// Read: @args = (int)
UC_CTL_CPU_MODEL,
// Request the edge of two TBs.
// Read: @args = (uint64_t, uint64_t, *uint64_t)
UC_CTL_TB_EDGE,
// Request a tb cache at a specific address
// Read: @args = (uint64_t)
UC_CTL_TB_REQUEST_CACHE,
// Remove a tb cache at a specific address
// Read: @args = (uint64_t)
UC_CTL_TB_REMOVE_CACHE
} uc_control_type;
#define uc_ctl_get_mode(uc, mode) \
uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_MODE, 1), (mode))
#define uc_ctl_get_page_size(uc, ptr) \
uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_PAGE_SIZE, 1, (ptr))
#define uc_ctl_set_page_size(uc, page_size) \
uc_ctl(uc, UC_CTL_WRITE(UC_CTL_UC_PAGE_SIZE, 1), (page_size))
#define uc_ctl_get_arch(uc, arch) \
uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_ARCH, 1), (arch))
#define uc_ctl_get_timeout(uc, ptr) \
uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_TIMEOUT, 1), (ptr))
#define uc_ctl_get_exists_cnt(uc, ptr) \
uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_EXITS_CNT, 1), (ptr))
#define uc_ctl_get_exists(uc, buffer, len) \
uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_EXITS, 2), (buffer), (len))
#define uc_ctl_set_exists(uc, buffer, len) \
uc_ctl(uc, UC_CTL_WRITE(UC_CTL_UC_EXITS, 2), (buffer), (len))
#define uc_ctl_get_cpu_model(uc, model) \
uc_ctl(uc, UC_CTL_READ(UC_CTL_CPU_MODEL, 1), (model))
#define uc_ctl_set_cpu_model(uc, model) \
uc_ctl(uc, UC_CTL_WRITE(UC_CTL_CPU_MODEL, 1), (model))
#define uc_ctl_remove_cache(uc, address) \
uc_ctl(uc, UC_CTL_WRITE(UC_CTL_TB_REMOVE_CACHE, 1), (address))
#define uc_ctl_request_cache(uc, address) \
uc_ctl(uc, UC_CTL_WRITE(UC_CTL_TB_REQUEST_CACHE, 1), (address))
#define uc_ctl_get_edge(uc, addr1, addr2, ptr) \
uc_ctl(uc, UC_CTL_READ_WRITE(UC_CTL_TB_EDGE, 3), (addr1), (addr2), (ptr))
// Opaque storage for CPU context, used with uc_context_*()
struct uc_context;
typedef struct uc_context uc_context;
@ -467,6 +569,20 @@ uc_err uc_close(uc_engine *uc);
UNICORN_EXPORT
uc_err uc_query(uc_engine *uc, uc_query_type type, size_t *result);
/*
Control internal states of engine.
Also see uc_ctl_* macro helpers for easy use.
@uc: handle returned by uc_open()
@option: control type.
@args: See uc_control_type for details about variadic arguments.
@return: error code of uc_err enum type (UC_ERR_*, see above)
*/
UNICORN_EXPORT
uc_err uc_ctl(uc_engine *uc, uc_control_type option, ...);
/*
Report the last error number when some API function fail.
Like glibc's errno, uc_errno might not retain its old value once accessed.

41
include/unicorn/x86.h
View File

@ -13,6 +13,47 @@ extern "C" {
#include "platform.h"
typedef enum uc_cpu_x86 {
UC_CPU_X86_QEMU64 = 0,
UC_CPU_X86_PHENOM,
UC_CPU_X86_CORE2DUO,
UC_CPU_X86_KVM64,
UC_CPU_X86_QEMU32,
UC_CPU_X86_KVM32,
UC_CPU_X86_COREDUO,
UC_CPU_X86_486,
UC_CPU_X86_PENTIUM,
UC_CPU_X86_PENTIUM2,
UC_CPU_X86_PENTIUM3,
UC_CPU_X86_ATHLON,
UC_CPU_X86_N270,
UC_CPU_X86_CONROE,
UC_CPU_X86_PENRYN,
UC_CPU_X86_NEHALEM,
UC_CPU_X86_WESTMERE,
UC_CPU_X86_SANDYBRIDGE,
UC_CPU_X86_IVYBRIDGE,
UC_CPU_X86_HASWELL,
UC_CPU_X86_BROADWELL,
UC_CPU_X86_SKYLAKE_CLIENT,
UC_CPU_X86_SKYLAKE_SERVER,
UC_CPU_X86_CASCADELAKE_SERVER,
UC_CPU_X86_COOPERLAKE,
UC_CPU_X86_ICELAKE_CLIENT,
UC_CPU_X86_ICELAKE_SERVER,
UC_CPU_X86_DENVERTON,
UC_CPU_X86_SNOWRIDGE,
UC_CPU_X86_KNIGHTSMILL,
UC_CPU_X86_OPTERON_G1,
UC_CPU_X86_OPTERON_G2,
UC_CPU_X86_OPTERON_G3,
UC_CPU_X86_OPTERON_G4,
UC_CPU_X86_OPTERON_G5,
UC_CPU_X86_EPYC,
UC_CPU_X86_DHYANA,
UC_CPU_X86_EPYC_ROME
} uc_cpu_x86;
// Memory-Management Register for instructions IDTR, GDTR, LDTR, TR.
// Borrow from SegmentCache in qemu/target-i386/cpu.h
typedef struct uc_x86_mmr {