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Merge QDucasse:riscv_extension_d

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Fix and close #1469

Fix test for riscv float points

Fix the riscv cpu config we left out
This commit is contained in:
lazymio
2021-11-03 13:20:46 +01:00
parent bcf85be86d
commit 09aa0f944f
2 changed files with 146 additions and 7 deletions
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19
qemu/target/riscv/cpu.c
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@ -364,6 +364,25 @@ RISCVCPU *cpu_riscv_init(struct uc_struct *uc, const char *cpu_model)
/* init RISCVCPUClass */
riscv_cpu_class_init(uc, cc, NULL);
/* init device properties*/
cpu->cfg.ext_i = true;
cpu->cfg.ext_e = false;
cpu->cfg.ext_g = true;
cpu->cfg.ext_m = true;
cpu->cfg.ext_a = true;
cpu->cfg.ext_f = true;
cpu->cfg.ext_d = true;
cpu->cfg.ext_c = true;
cpu->cfg.ext_s = true;
cpu->cfg.ext_u = true;
cpu->cfg.ext_h = false;
cpu->cfg.ext_counters = true;
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.priv_spec = "v1.11.0";
cpu->cfg.mmu = true;
cpu->cfg.pmp = true;
/* init CPUState */
cpu_common_initfn(uc, cs);