Uses latest qemu arm thumb load store stuff (#1021)
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committed by
Nguyen Anh Quynh

parent
333bfdf65e
commit
400a0ab309
@ -8532,34 +8532,29 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
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}
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} else {
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int address_offset;
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int load;
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int load = insn & (1 << 20);
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int wbit = insn & (1 << 21);
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int pbit = insn & (1 << 24);
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int doubleword = 0;
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/* Misc load/store */
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rn = (insn >> 16) & 0xf;
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rd = (insn >> 12) & 0xf;
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if (!load && (sh & 2)) {
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/* doubleword */
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ARCH(5TE);
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if (rd & 1) {
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/* UNPREDICTABLE; we choose to UNDEF */
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goto illegal_op;
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}
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load = (sh & 1) == 0;
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doubleword = 1;
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}
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addr = load_reg(s, rn);
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if (insn & (1 << 24))
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if (pbit)
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gen_add_datah_offset(s, insn, 0, addr);
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address_offset = 0;
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if (insn & (1 << 20)) {
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/* load */
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tmp = tcg_temp_new_i32(tcg_ctx);
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switch(sh) {
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case 1:
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gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
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break;
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case 2:
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gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
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break;
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default:
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case 3:
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gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
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break;
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}
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load = 1;
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} else if (sh & 2) {
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ARCH(5TE);
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/* doubleword */
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if (sh & 1) {
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if (doubleword) {
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if (!load) {
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/* store */
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tmp = load_reg(s, rd);
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gen_aa32_st32(s, tmp, addr, get_mem_index(s));
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@ -8568,7 +8563,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
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tmp = load_reg(s, rd + 1);
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gen_aa32_st32(s, tmp, addr, get_mem_index(s));
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tcg_temp_free_i32(tcg_ctx, tmp);
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load = 0;
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} else {
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/* load */
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tmp = tcg_temp_new_i32(tcg_ctx);
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@ -8578,24 +8572,37 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
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tmp = tcg_temp_new_i32(tcg_ctx);
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gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
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rd++;
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load = 1;
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}
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address_offset = -4;
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} else if (load) {
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/* load */
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tmp = tcg_temp_new_i32(tcg_ctx);
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switch(sh) {
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case 1:
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gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
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break;
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case 2:
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gen_aa32_ld8s(s, tmp, addr, get_mem_index(s));
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break;
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default:
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case 3:
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gen_aa32_ld16s(s, tmp, addr, get_mem_index(s));
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break;
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}
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} else {
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/* store */
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tmp = load_reg(s, rd);
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gen_aa32_st16(s, tmp, addr, get_mem_index(s));
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tcg_temp_free_i32(tcg_ctx, tmp);
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load = 0;
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}
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/* Perform base writeback before the loaded value to
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ensure correct behavior with overlapping index registers.
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ldrd with base writeback is is undefined if the
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destination and index registers overlap. */
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if (!(insn & (1 << 24))) {
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if (!pbit) {
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gen_add_datah_offset(s, insn, address_offset, addr);
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store_reg(s, rn, addr);
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} else if (insn & (1 << 21)) {
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} else if (wbit) {
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if (address_offset)
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tcg_gen_addi_i32(tcg_ctx, addr, addr, address_offset);
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store_reg(s, rn, addr);
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