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Added MIPS support and projects for all samples.

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This commit is contained in:
xorstream
2017-01-23 01:05:08 +11:00
parent 1756ae770b
commit 72a497bc14
55 changed files with 3295 additions and 772 deletions
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24
qemu/target-mips/cpu.c
View File

@ -146,14 +146,22 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
void mips_cpu_register_types(void *opaque)
{
const TypeInfo mips_cpu_type_info = {
.name = TYPE_MIPS_CPU,
.parent = TYPE_CPU,
.instance_userdata = opaque,
.instance_size = sizeof(MIPSCPU),
.instance_init = mips_cpu_initfn,
.abstract = false,
.class_size = sizeof(MIPSCPUClass),
.class_init = mips_cpu_class_init,
TYPE_MIPS_CPU,
TYPE_CPU,
sizeof(MIPSCPUClass),
sizeof(MIPSCPU),
opaque,
mips_cpu_initfn,
NULL,
NULL,
mips_cpu_class_init,
NULL,
NULL,
false,
};
type_register_static(opaque, &mips_cpu_type_info);

2
qemu/target-mips/cpu.h
View File

@ -571,7 +571,7 @@ struct CPUMIPSState {
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */
CPU_COMMON
CPU_COMMON
/* Fields from here on are preserved across CPU reset. */
CPUMIPSMVPContext *mvp;

2
qemu/target-mips/dsp_helper.c
View File

@ -3678,7 +3678,7 @@ void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env)
void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env)
{
return cpu_wrdsp(rs, mask_num, env);
cpu_wrdsp(rs, mask_num, env);
}
uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env)

75
qemu/target-mips/helper.c
View File

@ -377,43 +377,44 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int r
#endif
static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_RESET] = "reset",
[EXCP_SRESET] = "soft reset",
[EXCP_DSS] = "debug single step",
[EXCP_DINT] = "debug interrupt",
[EXCP_NMI] = "non-maskable interrupt",
[EXCP_MCHECK] = "machine check",
[EXCP_EXT_INTERRUPT] = "interrupt",
[EXCP_DFWATCH] = "deferred watchpoint",
[EXCP_DIB] = "debug instruction breakpoint",
[EXCP_IWATCH] = "instruction fetch watchpoint",
[EXCP_AdEL] = "address error load",
[EXCP_AdES] = "address error store",
[EXCP_TLBF] = "TLB refill",
[EXCP_IBE] = "instruction bus error",
[EXCP_DBp] = "debug breakpoint",
[EXCP_SYSCALL] = "syscall",
[EXCP_BREAK] = "break",
[EXCP_CpU] = "coprocessor unusable",
[EXCP_RI] = "reserved instruction",
[EXCP_OVERFLOW] = "arithmetic overflow",
[EXCP_TRAP] = "trap",
[EXCP_FPE] = "floating point",
[EXCP_DDBS] = "debug data break store",
[EXCP_DWATCH] = "data watchpoint",
[EXCP_LTLBL] = "TLB modify",
[EXCP_TLBL] = "TLB load",
[EXCP_TLBS] = "TLB store",
[EXCP_DBE] = "data bus error",
[EXCP_DDBL] = "debug data break load",
[EXCP_THREAD] = "thread",
[EXCP_MDMX] = "MDMX",
[EXCP_C2E] = "precise coprocessor 2",
[EXCP_CACHE] = "cache error",
[EXCP_TLBXI] = "TLB execute-inhibit",
[EXCP_TLBRI] = "TLB read-inhibit",
[EXCP_MSADIS] = "MSA disabled",
[EXCP_MSAFPE] = "MSA floating point",
"reset",
"soft reset",
"debug single step",
"debug interrupt",
"debug data break load",
"debug data break store",
"non-maskable interrupt",
"machine check",
"interrupt",
"deferred watchpoint",
"debug instruction breakpoint",
"instruction fetch watchpoint",
"address error load",
"address error store",
"TLB refill",
"instruction bus error",
"debug breakpoint",
"syscall",
"break",
"coprocessor unusable",
"reserved instruction",
"arithmetic overflow",
"trap",
"floating point",
"data watchpoint",
"TLB modify",
"TLB load",
"TLB store",
"data bus error",
"thread",
"MDMX",
"precise coprocessor 2",
"cache error",
"DSP disabled",
"MSA disabled",
"MSA floating point",
"TLB execute-inhibit",
"TLB read-inhibit",
};
target_ulong exception_resume_pc (CPUMIPSState *env)

12
qemu/target-mips/msa_helper.c
View File

@ -21,7 +21,7 @@
#include "exec/helper-proto.h"
/* Data format min and max values */
#define DF_BITS(df) (1 << ((df) + 3))
#define DF_BITS(df) ((uint64_t)1 << ((df) + 3))
#define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
#define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
@ -29,8 +29,8 @@
#define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
#define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
#define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
#define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
#define DF_MAX_UINT(df) (uint64_t)((0-1ULL) >> (64 - DF_BITS(df)))
#define M_MAX_UINT(m) (uint64_t)((0-1ULL) >> (64 - (m)))
#define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
#define SIGNED(x, df) \
@ -786,7 +786,7 @@ static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int64_t q_min = DF_MIN_INT(df);
int64_t q_max = DF_MAX_INT(df);
int64_t r_bit = 1 << (DF_BITS(df) - 2);
int64_t r_bit = (int64_t)1 << (DF_BITS(df) - 2);
if (arg1 == q_min && arg2 == q_min) {
return q_max;
@ -984,7 +984,7 @@ static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t q_max = DF_MAX_INT(df);
int64_t q_min = DF_MIN_INT(df);
int64_t r_bit = 1 << (DF_BITS(df) - 2);
int64_t r_bit = (int64_t)1 << (DF_BITS(df) - 2);
q_prod = arg1 * arg2;
q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
@ -999,7 +999,7 @@ static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t q_max = DF_MAX_INT(df);
int64_t q_min = DF_MIN_INT(df);
int64_t r_bit = 1 << (DF_BITS(df) - 2);
int64_t r_bit = (int64_t)1 << (DF_BITS(df) - 2);
q_prod = arg1 * arg2;
q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);

102
qemu/target-mips/translate.c
View File

@ -5328,7 +5328,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
case 0 ... 7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_1e0i(tcg_ctx, mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@ -5338,7 +5338,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
case 0 ...7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@ -5458,7 +5458,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
case 0 ... 3:
case 0: case 1: case 2: case 3:
tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */
rn = "CacheErr";
break;
@ -5524,7 +5524,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
case 2 ... 7:
case 2: case 3: case 4: case 5: case 6: case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -5947,7 +5947,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
case 0 ... 7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@ -5957,7 +5957,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
case 0 ... 7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@ -6088,7 +6088,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
case 0 ... 3:
case 0: case 1: case 2: case 3:
/* ignored */
rn = "CacheErr";
break;
@ -6154,7 +6154,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
case 2 ... 7:
case 2: case 3: case 4: case 5: case 6: case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -6572,7 +6572,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
case 0 ... 7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_1e0i(tcg_ctx, dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@ -6582,7 +6582,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
case 0 ... 7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@ -6699,7 +6699,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 27:
switch (sel) {
/* ignored */
case 0 ... 3:
case 0: case 1: case 2: case 3:
tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */
rn = "CacheErr";
break;
@ -6764,7 +6764,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
case 2 ... 7:
case 2: case 3: case 4: case 5: case 6: case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -7191,7 +7191,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
case 0 ... 7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@ -7201,7 +7201,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 19:
switch (sel) {
case 0 ... 7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@ -7328,7 +7328,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
case 0 ... 3:
case 0: case 1: case 2: case 3:
/* ignored */
rn = "CacheErr";
break;
@ -7394,7 +7394,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
case 2 ... 7:
case 2: case 3: case 4: case 5: case 6: case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -7530,7 +7530,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
break;
case 16:
switch (sel) {
case 0 ... 7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_mftc0_configx(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_const_tl(tcg_ctx, sel));
break;
default:
@ -16208,7 +16208,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free(tcg_ctx, t0);
}
break;
case OPC_MULT ... OPC_DIVU:
case OPC_MULT: case OPC_MULTU: case OPC_DIV: case OPC_DIVU:
op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) {
case R6_OPC_MUL:
@ -16274,7 +16274,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
generate_exception(ctx, EXCP_RI);
}
break;
case OPC_DMULT ... OPC_DDIVU:
case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU:
op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) {
case R6_OPC_DMUL:
@ -16353,7 +16353,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_muldiv(ctx, op1, 0, rs, rt);
break;
#if defined(TARGET_MIPS64)
case OPC_DMULT ... OPC_DDIVU:
case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_muldiv(ctx, op1, 0, rs, rt);
@ -16422,7 +16422,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
case OPC_ADD ... OPC_SUBU:
case OPC_ADD: case OPC_ADDU: case OPC_SUB: case OPC_SUBU:
gen_arith(ctx, op1, rd, rs, rt);
break;
case OPC_SLLV: /* Shifts */
@ -16458,7 +16458,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
case OPC_JALR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
break;
case OPC_TGE ... OPC_TEQ: /* Traps */
case OPC_TGE: case OPC_TGEU: case OPC_TLT: case OPC_TLTU: case OPC_TEQ:
case OPC_TNE:
gen_trap(ctx, op1, rs, rt, -1);
break;
@ -16533,7 +16533,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
case OPC_DADD ... OPC_DSUBU:
case OPC_DADD: case OPC_DADDU: case OPC_DSUB: case OPC_DSUBU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith(ctx, op1, rd, rs, rt);
@ -16591,8 +16591,8 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL2(ctx->opcode);
switch (op1) {
case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
case OPC_MSUB ... OPC_MSUBU:
case OPC_MADD: case OPC_MADDU:
case OPC_MSUB: case OPC_MSUBU:
check_insn(ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
@ -16683,16 +16683,17 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_BSHFL:
{
if (rd == 0) {
TCGv t0;
if (rd == 0) {
/* Treat as NOP. */
break;
}
TCGv t0 = tcg_temp_new(tcg_ctx);
t0 = tcg_temp_new(tcg_ctx);
gen_load_gpr(ctx, t0, rt);
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_ALIGN ... OPC_ALIGN_END:
case OPC_ALIGN: case OPC_ALIGN_END:
sa &= 3;
if (sa == 0) {
tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0);
@ -16728,16 +16729,17 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
case OPC_DBSHFL:
check_mips_64(ctx);
{
if (rd == 0) {
TCGv t0;
if (rd == 0) {
/* Treat as NOP. */
break;
}
TCGv t0 = tcg_temp_new(tcg_ctx);
t0 = tcg_temp_new(tcg_ctx);
gen_load_gpr(ctx, t0, rt);
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DALIGN ... OPC_DALIGN_END:
case OPC_DALIGN: case OPC_DALIGN_END:
sa &= 7;
if (sa == 0) {
tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0);
@ -16778,9 +16780,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
case OPC_MOD_G_2E ... OPC_MODU_G_2E:
case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
case OPC_DIV_G_2E: case OPC_DIVU_G_2E:
case OPC_MOD_G_2E: case OPC_MODU_G_2E:
case OPC_MULT_G_2E: case OPC_MULTU_G_2E:
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */
if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
@ -17045,9 +17047,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
case OPC_DDIV_G_2E: case OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E:
case OPC_DMOD_G_2E: case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@ -17310,7 +17312,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
case OPC_BSHFL:
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_ALIGN ... OPC_ALIGN_END:
case OPC_ALIGN: case OPC_ALIGN_END:
case OPC_BITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
@ -17322,16 +17324,16 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
check_insn(ctx, ISA_MIPS64R2);
case OPC_DEXTM: case OPC_DEXTU: case OPC_DEXT:
case OPC_DINSM: case OPC_DINSU: case OPC_DINS:
check_insn(ctx, ISA_MIPS64R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
case OPC_DBSHFL:
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DALIGN ... OPC_DALIGN_END:
case OPC_DALIGN: case OPC_DALIGN_END:
case OPC_DBITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
@ -18585,7 +18587,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
}
break;
case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
case OPC_TGEI: case OPC_TGEIU: case OPC_TLTI: case OPC_TLTIU: case OPC_TEQI: /* REGIMM traps */
case OPC_TNEI:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_trap(ctx, op1, rs, -1, imm);
@ -18643,7 +18645,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
gen_cp0(env, ctx, op1, rt, rd);
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_C0_FIRST ... OPC_C0_LAST:
case OPC_C0_FIRST: case OPC_C0_LAST:
#ifndef CONFIG_USER_ONLY
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
#endif /* !CONFIG_USER_ONLY */
@ -18738,7 +18740,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
case OPC_XORI:
gen_logic_imm(ctx, op, rt, rs, imm);
break;
case OPC_J ... OPC_JAL: /* Jump */
case OPC_J: case OPC_JAL: /* Jump */
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
break;
@ -18800,14 +18802,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
case OPC_LWR:
case OPC_LL:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_LB ... OPC_LH:
case OPC_LW ... OPC_LHU:
case OPC_LB: case OPC_LH:
case OPC_LW: case OPC_LBU: case OPC_LHU:
gen_ld(ctx, op, rt, rs, imm);
break;
case OPC_SWL:
case OPC_SWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_SB ... OPC_SH:
case OPC_SB: case OPC_SH:
case OPC_SW:
gen_st(ctx, op, rt, rs, imm);
break;
@ -19065,7 +19067,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
case OPC_LDL ... OPC_LDR:
case OPC_LDL: case OPC_LDR:
case OPC_LLD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_LWU:
@ -19074,7 +19076,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
check_mips_64(ctx);
gen_ld(ctx, op, rt, rs, imm);
break;
case OPC_SDL ... OPC_SDR:
case OPC_SDL: case OPC_SDR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_SD:
check_insn(ctx, ISA_MIPS3);

872
qemu/target-mips/translate_init.c
View File

File diff suppressed because it is too large Load Diff

10
qemu/target-mips/unicorn.c
View File

@ -42,10 +42,11 @@ static void mips_set_pc(struct uc_struct *uc, uint64_t address)
void mips_release(void *ctx);
void mips_release(void *ctx)
{
int i;
MIPSCPU* cpu;
int i;
TCGContext *tcg_ctx = (TCGContext *) ctx;
release_common(ctx);
MIPSCPU* cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu);
cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu);
g_free(cpu->env.tlb);
g_free(cpu->env.mvp);
@ -68,8 +69,9 @@ void mips_release(void *ctx)
void mips_reg_reset(struct uc_struct *uc)
{
(void)uc;
CPUArchState *env = uc->cpu->env_ptr;
CPUArchState *env;
(void)uc;
env = uc->cpu->env_ptr;
memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr));
env->active_tc.PC = 0;