fix some gcc warnings
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@ -163,8 +163,8 @@ static void aarch64_cpu_finalizefn(struct uc_struct *uc, Object *obj, void *opaq
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static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
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static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
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{
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{
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CPUARMState *env = cs->env_ptr;
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//CPUARMState *env = cs->env_ptr;
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ARMCPU *cpu = ARM_CPU(env->uc, cs);
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ARMCPU *cpu = ARM_CPU(NULL, cs);
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/* It's OK to look at env for the current mode here, because it's
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/* It's OK to look at env for the current mode here, because it's
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* never possible for an AArch64 TB to chain to an AArch32 TB.
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* never possible for an AArch64 TB to chain to an AArch32 TB.
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* (Otherwise we would need to use synchronize_from_tb instead.)
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* (Otherwise we would need to use synchronize_from_tb instead.)
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@ -2692,8 +2692,8 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
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// on msvc, so is replaced with separate versions for the shift to perform.
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// on msvc, so is replaced with separate versions for the shift to perform.
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//#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
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//#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
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#if 0
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#if 0
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//#define VFP_SREG(insn, bigbit, smallbit) \
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#define VFP_SREG(insn, bigbit, smallbit) \
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// ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
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((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
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#endif
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#endif
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#define VFP_REG_SHR_NEG(insn, n) ((insn) << -(n))
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#define VFP_REG_SHR_NEG(insn, n) ((insn) << -(n))
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