Sparc support added. (#734)
* Fix for MIPS issue. * Sparc support added.
This commit is contained in:
xorstream
committed by
Nguyen Anh Quynh
Nguyen Anh Quynh
parent
69ae8f7987
commit
a40921ce32
@ -158,338 +158,378 @@ void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
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static const sparc_def_t sparc_defs[] = {
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#ifdef TARGET_SPARC64
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{
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.name = "Fujitsu Sparc64",
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.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 4,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES,
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"Fujitsu Sparc64",
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((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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4,
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4,
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},
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{
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.name = "Fujitsu Sparc64 III",
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.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 5,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES,
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"Fujitsu Sparc64 III",
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((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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5,
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4,
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},
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{
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.name = "Fujitsu Sparc64 IV",
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.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"Fujitsu Sparc64 IV",
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((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "Fujitsu Sparc64 V",
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.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"Fujitsu Sparc64 V",
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((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "TI UltraSparc I",
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.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"TI UltraSparc I",
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((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "TI UltraSparc II",
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.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"TI UltraSparc II",
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((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "TI UltraSparc IIi",
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.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"TI UltraSparc IIi",
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((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "TI UltraSparc IIe",
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.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"TI UltraSparc IIe",
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((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "Sun UltraSparc III",
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.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"Sun UltraSparc III",
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((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "Sun UltraSparc III Cu",
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.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"Sun UltraSparc III Cu",
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((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
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0x00000000,
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mmu_us_3,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "Sun UltraSparc IIIi",
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.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"Sun UltraSparc IIIi",
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((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "Sun UltraSparc IV",
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.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_4,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"Sun UltraSparc IV",
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((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
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0x00000000,
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mmu_us_4,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "Sun UltraSparc IV+",
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.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
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"Sun UltraSparc IV+",
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((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
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8,
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5,
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},
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{
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.name = "Sun UltraSparc IIIi+",
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.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"Sun UltraSparc IIIi+",
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((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
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0x00000000,
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mmu_us_3,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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{
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.name = "Sun UltraSparc T1",
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"Sun UltraSparc T1",
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/* defined in sparc_ifu_fdp.v and ctu.h */
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.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
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0x00000000,
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mmu_sun4v,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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8,
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6,
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},
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{
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.name = "Sun UltraSparc T2",
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"Sun UltraSparc T2",
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/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
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.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
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0x00000000,
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mmu_sun4v,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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8,
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6,
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},
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{
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.name = "NEC UltraSparc I",
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.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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"NEC UltraSparc I",
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((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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0x00000000,
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mmu_us_12,
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0,0,0,0,0,0,
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CPU_DEFAULT_FEATURES,
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8,
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5,
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},
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#else
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{
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.name = "Fujitsu MB86904",
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.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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"Fujitsu MB86904",
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0x04 << 24, /* Impl 0, ver 4 */
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4 << 17, /* FPU version 4 (Meiko) */
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0x04 << 24, /* Impl 0, ver 4 */
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0x00004000,
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0x00ffffc0,
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0x000000ff,
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0x00016fff,
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0x00ffffff,
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0,
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CPU_DEFAULT_FEATURES,
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8,
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0,
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},
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{
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.name = "Fujitsu MB86907",
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.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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"Fujitsu MB86907",
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0x05 << 24, /* Impl 0, ver 5 */
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4 << 17, /* FPU version 4 (Meiko) */
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0x05 << 24, /* Impl 0, ver 5 */
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0x00004000,
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0xffffffc0,
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0x000000ff,
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0x00016fff,
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0xffffffff,
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0,
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CPU_DEFAULT_FEATURES,
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8,
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0,
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},
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{
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.name = "TI MicroSparc I",
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.iu_version = 0x41000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x41000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x007ffff0,
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.mmu_cxr_mask = 0x0000003f,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x0000003f,
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.nwindows = 7,
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.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
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CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
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CPU_FEATURE_FMUL,
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"TI MicroSparc I",
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0x41000000,
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4 << 17,
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0x41000000,
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0x00004000,
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0x007ffff0,
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0x0000003f,
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0x00016fff,
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0x0000003f,
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0,
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CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
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CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
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CPU_FEATURE_FMUL,
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7,
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0,
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},
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{
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.name = "TI MicroSparc II",
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x02000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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"TI MicroSparc II",
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0x42000000,
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4 << 17,
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0x02000000,
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0x00004000,
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0x00ffffc0,
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0x000000ff,
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0x00016fff,
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0x00ffffff,
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0,
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CPU_DEFAULT_FEATURES,
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8,
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0,
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},
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{
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.name = "TI MicroSparc IIep",
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x04000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016bff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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"TI MicroSparc IIep",
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0x42000000,
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4 << 17,
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0x04000000,
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0x00004000,
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0x00ffffc0,
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0x000000ff,
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0x00016bff,
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0x00ffffff,
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0,
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CPU_DEFAULT_FEATURES,
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8,
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0,
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},
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{
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.name = "TI SuperSparc 40", /* STP1020NPGA */
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.iu_version = 0x41000000, /* SuperSPARC 2.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
"TI SuperSparc 40", /* STP1020NPGA */
|
||||
0x41000000, /* SuperSPARC 2.x */
|
||||
0 << 17,
|
||||
0x00000800, /* SuperSPARC 2.x, no MXCC */
|
||||
0x00002000,
|
||||
0xffffffc0,
|
||||
0x0000ffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0,
|
||||
CPU_DEFAULT_FEATURES,
|
||||
8,
|
||||
0,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc 50", /* STP1020PGA */
|
||||
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
"TI SuperSparc 50", /* STP1020PGA */
|
||||
0x40000000, /* SuperSPARC 3.x */
|
||||
0 << 17,
|
||||
0x01000800, /* SuperSPARC 3.x, no MXCC */
|
||||
0x00002000,
|
||||
0xffffffc0,
|
||||
0x0000ffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0,
|
||||
CPU_DEFAULT_FEATURES,
|
||||
8,
|
||||
0,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc 51",
|
||||
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.mxcc_version = 0x00000104,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
"TI SuperSparc 51",
|
||||
0x40000000, /* SuperSPARC 3.x */
|
||||
0 << 17,
|
||||
0x01000000, /* SuperSPARC 3.x, MXCC */
|
||||
0x00002000,
|
||||
0xffffffc0,
|
||||
0x0000ffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0x00000104,
|
||||
CPU_DEFAULT_FEATURES,
|
||||
8,
|
||||
0,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc 60", /* STP1020APGA */
|
||||
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
"TI SuperSparc 60", /* STP1020APGA */
|
||||
0x40000000, /* SuperSPARC 3.x */
|
||||
0 << 17,
|
||||
0x01000800, /* SuperSPARC 3.x, no MXCC */
|
||||
0x00002000,
|
||||
0xffffffc0,
|
||||
0x0000ffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0,
|
||||
CPU_DEFAULT_FEATURES,
|
||||
8,
|
||||
0,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc 61",
|
||||
.iu_version = 0x44000000, /* SuperSPARC 3.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.mxcc_version = 0x00000104,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
"TI SuperSparc 61",
|
||||
0x44000000, /* SuperSPARC 3.x */
|
||||
0 << 17,
|
||||
0x01000000, /* SuperSPARC 3.x, MXCC */
|
||||
0x00002000,
|
||||
0xffffffc0,
|
||||
0x0000ffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0x00000104,
|
||||
CPU_DEFAULT_FEATURES,
|
||||
8,
|
||||
0,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc II",
|
||||
.iu_version = 0x40000000, /* SuperSPARC II 1.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.mxcc_version = 0x00000104,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
"TI SuperSparc II",
|
||||
0x40000000, /* SuperSPARC II 1.x */
|
||||
0 << 17,
|
||||
0x08000000, /* SuperSPARC II 1.x, MXCC */
|
||||
0x00002000,
|
||||
0xffffffc0,
|
||||
0x0000ffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0x00000104,
|
||||
CPU_DEFAULT_FEATURES,
|
||||
8,
|
||||
0,
|
||||
},
|
||||
{
|
||||
.name = "LEON2",
|
||||
.iu_version = 0xf2000000,
|
||||
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
||||
.mmu_version = 0xf2000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
|
||||
"LEON2",
|
||||
0xf2000000,
|
||||
4 << 17, /* FPU version 4 (Meiko) */
|
||||
0xf2000000,
|
||||
0x00004000,
|
||||
0x007ffff0,
|
||||
0x0000003f,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0,
|
||||
CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
|
||||
8,
|
||||
0,
|
||||
},
|
||||
{
|
||||
.name = "LEON3",
|
||||
.iu_version = 0xf3000000,
|
||||
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
||||
.mmu_version = 0xf3000000,
|
||||
.mmu_bm = 0x00000000,
|
||||
.mmu_ctpr_mask = 0xfffffffc,
|
||||
.mmu_cxr_mask = 0x000000ff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
|
||||
CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
|
||||
CPU_FEATURE_CASA,
|
||||
"LEON3",
|
||||
0xf3000000,
|
||||
4 << 17, /* FPU version 4 (Meiko) */
|
||||
0xf3000000,
|
||||
0x00000000,
|
||||
0xfffffffc,
|
||||
0x000000ff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0,
|
||||
CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
|
||||
CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
|
||||
CPU_FEATURE_CASA,
|
||||
8,
|
||||
0,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
@ -857,16 +897,25 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
|
||||
|
||||
void sparc_cpu_register_types(void *opaque)
|
||||
{
|
||||
TypeInfo sparc_cpu_type_info = {
|
||||
.name = TYPE_SPARC_CPU,
|
||||
.parent = TYPE_CPU,
|
||||
.instance_userdata = opaque,
|
||||
.instance_size = sizeof(SPARCCPU),
|
||||
.instance_init = sparc_cpu_initfn,
|
||||
.instance_finalize = sparc_cpu_uninitfn,
|
||||
.abstract = false,
|
||||
.class_size = sizeof(SPARCCPUClass),
|
||||
.class_init = sparc_cpu_class_init,
|
||||
const TypeInfo sparc_cpu_type_info = {
|
||||
TYPE_SPARC_CPU,
|
||||
TYPE_CPU,
|
||||
|
||||
sizeof(SPARCCPUClass),
|
||||
sizeof(SPARCCPU),
|
||||
opaque,
|
||||
|
||||
sparc_cpu_initfn,
|
||||
NULL,
|
||||
sparc_cpu_uninitfn,
|
||||
|
||||
NULL,
|
||||
|
||||
sparc_cpu_class_init,
|
||||
NULL,
|
||||
NULL,
|
||||
|
||||
false,
|
||||
};
|
||||
|
||||
//printf(">>> sparc_cpu_register_types\n");
|
||||
|
||||
Reference in New Issue
Block a user