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Merge pull request #1462 from bet4it/const

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Update Rust constants to Unicorn2
This commit is contained in:
lazymio
2021-10-16 17:10:59 +02:00
committed by GitHub
parent 0b7873f5a6 5a97bf7f8f
commit fde59f38ce
10 changed files with 505 additions and 286 deletions
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30
bindings/rust/src/arm.rs
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@ -123,8 +123,31 @@ pub enum RegisterARM {
MSP = 115, MSP = 115,
PSP = 116, PSP = 116,
CONTROL = 117, CONTROL = 117,
XPSR = 118, IAPSR = 118,
ENDING = 119, EAPSR = 119,
XPSR = 120,
EPSR = 121,
IEPSR = 122,
PRIMASK = 123,
BASEPRI = 124,
BASEPRI_MAX = 125,
FAULTMASK = 126,
APSR_NZCVQ = 127,
APSR_G = 128,
APSR_NZCVQG = 129,
IAPSR_NZCVQ = 130,
IAPSR_G = 131,
IAPSR_NZCVQG = 132,
EAPSR_NZCVQ = 133,
EAPSR_G = 134,
EAPSR_NZCVQG = 135,
XPSR_NZCVQ = 136,
XPSR_G = 137,
XPSR_NZCVQG = 138,
ENDING = 139,
}
impl RegisterARM {
// alias registers // alias registers
// (assoc) R13 = 12, // (assoc) R13 = 12,
// (assoc) R14 = 10, // (assoc) R14 = 10,
@ -133,9 +156,6 @@ pub enum RegisterARM {
// (assoc) SL = 76, // (assoc) SL = 76,
// (assoc) FP = 77, // (assoc) FP = 77,
// (assoc) IP = 78, // (assoc) IP = 78,
}
impl RegisterARM {
pub const R13: RegisterARM = RegisterARM::SP; pub const R13: RegisterARM = RegisterARM::SP;
pub const R14: RegisterARM = RegisterARM::LR; pub const R14: RegisterARM = RegisterARM::LR;
pub const R15: RegisterARM = RegisterARM::PC; pub const R15: RegisterARM = RegisterARM::PC;

1
bindings/rust/src/arm64.rs
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@ -1,4 +1,5 @@
#![allow(non_camel_case_types)] #![allow(non_camel_case_types)]
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
// ARM64 registers // ARM64 registers
#[repr(C)] #[repr(C)]

3
bindings/rust/src/lib.rs
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@ -35,9 +35,10 @@ mod arm64;
mod m68k; mod m68k;
mod mips; mod mips;
mod ppc; mod ppc;
mod riscv;
mod sparc; mod sparc;
mod x86; mod x86;
pub use crate::{arm::*, arm64::*, m68k::*, mips::*, ppc::*, sparc::*, x86::*}; pub use crate::{arm::*, arm64::*, m68k::*, mips::*, ppc::*, riscv::*, sparc::*, x86::*};
use ffi::uc_handle; use ffi::uc_handle;
use std::collections::HashMap; use std::collections::HashMap;

1
bindings/rust/src/m68k.rs
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@ -21,4 +21,5 @@ pub enum RegisterM68K {
D7, D7,
SR, SR,
PC, PC,
ENDING,
} }

10
bindings/rust/src/mips.rs
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@ -1,4 +1,5 @@
#![allow(non_camel_case_types)] #![allow(non_camel_case_types)]
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
// MIPS registers // MIPS registers
#[repr(C)] #[repr(C)]
@ -155,7 +156,11 @@ pub enum RegisterMIPS {
MPL2 = 136, MPL2 = 136,
CP0_CONFIG3 = 137, CP0_CONFIG3 = 137,
CP0_USERLOCAL = 138, CP0_USERLOCAL = 138,
ENDING = 139, CP0_STATUS = 139,
ENDING = 140,
}
impl RegisterMIPS {
// alias registers // alias registers
// (assoc) ZERO = 2, // (assoc) ZERO = 2,
// (assoc) AT = 3, // (assoc) AT = 3,
@ -198,9 +203,6 @@ pub enum RegisterMIPS {
// (assoc) LO1 = 46, // (assoc) LO1 = 46,
// (assoc) LO2 = 47, // (assoc) LO2 = 47,
// (assoc) LO3 = 48, // (assoc) LO3 = 48,
}
impl RegisterMIPS {
pub const ZERO: RegisterMIPS = RegisterMIPS::GPR0; pub const ZERO: RegisterMIPS = RegisterMIPS::GPR0;
pub const AT: RegisterMIPS = RegisterMIPS::GPR1; pub const AT: RegisterMIPS = RegisterMIPS::GPR1;
pub const V0: RegisterMIPS = RegisterMIPS::GPR2; pub const V0: RegisterMIPS = RegisterMIPS::GPR2;

213
bindings/rust/src/riscv.rs Normal file
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@ -0,0 +1,213 @@
#![allow(non_camel_case_types)]
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
// RISCV registers
#[repr(C)]
#[derive(PartialEq, Debug, Clone, Copy)]
pub enum RegisterRISCV {
INVALID = 0,
// General purpose registers
X0 = 1,
X1 = 2,
X2 = 3,
X3 = 4,
X4 = 5,
X5 = 6,
X6 = 7,
X7 = 8,
X8 = 9,
X9 = 10,
X10 = 11,
X11 = 12,
X12 = 13,
X13 = 14,
X14 = 15,
X15 = 16,
X16 = 17,
X17 = 18,
X18 = 19,
X19 = 20,
X20 = 21,
X21 = 22,
X22 = 23,
X23 = 24,
X24 = 25,
X25 = 26,
X26 = 27,
X27 = 28,
X28 = 29,
X29 = 30,
X30 = 31,
X31 = 32,
// Floating-point registers
F0 = 33,
F1 = 34,
F2 = 35,
F3 = 36,
F4 = 37,
F5 = 38,
F6 = 39,
F7 = 40,
F8 = 41,
F9 = 42,
F10 = 43,
F11 = 44,
F12 = 45,
F13 = 46,
F14 = 47,
F15 = 48,
F16 = 49,
F17 = 50,
F18 = 51,
F19 = 52,
F20 = 53,
F21 = 54,
F22 = 55,
F23 = 56,
F24 = 57,
F25 = 58,
F26 = 59,
F27 = 60,
F28 = 61,
F29 = 62,
F30 = 63,
F31 = 64,
PC = 65,
ENDING = 66,
}
impl RegisterRISCV {
// Alias registers
// (assoc) ZERO = 1,
// (assoc) RA = 2,
// (assoc) SP = 3,
// (assoc) GP = 4,
// (assoc) TP = 5,
// (assoc) T0 = 6,
// (assoc) T1 = 7,
// (assoc) T2 = 8,
// (assoc) S0 = 9,
// (assoc) FP = 9,
// (assoc) S1 = 10,
// (assoc) A0 = 11,
// (assoc) A1 = 12,
// (assoc) A2 = 13,
// (assoc) A3 = 14,
// (assoc) A4 = 15,
// (assoc) A5 = 16,
// (assoc) A6 = 17,
// (assoc) A7 = 18,
// (assoc) S2 = 19,
// (assoc) S3 = 20,
// (assoc) S4 = 21,
// (assoc) S5 = 22,
// (assoc) S6 = 23,
// (assoc) S7 = 24,
// (assoc) S8 = 25,
// (assoc) S9 = 26,
// (assoc) S10 = 27,
// (assoc) S11 = 28,
// (assoc) T3 = 29,
// (assoc) T4 = 30,
// (assoc) T5 = 31,
// (assoc) T6 = 32,
// (assoc) FT0 = 33,
// (assoc) FT1 = 34,
// (assoc) FT2 = 35,
// (assoc) FT3 = 36,
// (assoc) FT4 = 37,
// (assoc) FT5 = 38,
// (assoc) FT6 = 39,
// (assoc) FT7 = 40,
// (assoc) FS0 = 41,
// (assoc) FS1 = 42,
// (assoc) FA0 = 43,
// (assoc) FA1 = 44,
// (assoc) FA2 = 45,
// (assoc) FA3 = 46,
// (assoc) FA4 = 47,
// (assoc) FA5 = 48,
// (assoc) FA6 = 49,
// (assoc) FA7 = 50,
// (assoc) FS2 = 51,
// (assoc) FS3 = 52,
// (assoc) FS4 = 53,
// (assoc) FS5 = 54,
// (assoc) FS6 = 55,
// (assoc) FS7 = 56,
// (assoc) FS8 = 57,
// (assoc) FS9 = 58,
// (assoc) FS10 = 59,
// (assoc) FS11 = 60,
// (assoc) FT8 = 61,
// (assoc) FT9 = 62,
// (assoc) FT10 = 63,
// (assoc) FT11 = 64,
pub const ZERO: RegisterRISCV = RegisterRISCV::X0;
pub const RA: RegisterRISCV = RegisterRISCV::X1;
pub const SP: RegisterRISCV = RegisterRISCV::X2;
pub const GP: RegisterRISCV = RegisterRISCV::X3;
pub const TP: RegisterRISCV = RegisterRISCV::X4;
pub const T0: RegisterRISCV = RegisterRISCV::X5;
pub const T1: RegisterRISCV = RegisterRISCV::X6;
pub const T2: RegisterRISCV = RegisterRISCV::X7;
pub const S0: RegisterRISCV = RegisterRISCV::X8;
pub const FP: RegisterRISCV = RegisterRISCV::X8;
pub const S1: RegisterRISCV = RegisterRISCV::X9;
pub const A0: RegisterRISCV = RegisterRISCV::X10;
pub const A1: RegisterRISCV = RegisterRISCV::X11;
pub const A2: RegisterRISCV = RegisterRISCV::X12;
pub const A3: RegisterRISCV = RegisterRISCV::X13;
pub const A4: RegisterRISCV = RegisterRISCV::X14;
pub const A5: RegisterRISCV = RegisterRISCV::X15;
pub const A6: RegisterRISCV = RegisterRISCV::X16;
pub const A7: RegisterRISCV = RegisterRISCV::X17;
pub const S2: RegisterRISCV = RegisterRISCV::X18;
pub const S3: RegisterRISCV = RegisterRISCV::X19;
pub const S4: RegisterRISCV = RegisterRISCV::X20;
pub const S5: RegisterRISCV = RegisterRISCV::X21;
pub const S6: RegisterRISCV = RegisterRISCV::X22;
pub const S7: RegisterRISCV = RegisterRISCV::X23;
pub const S8: RegisterRISCV = RegisterRISCV::X24;
pub const S9: RegisterRISCV = RegisterRISCV::X25;
pub const S10: RegisterRISCV = RegisterRISCV::X26;
pub const S11: RegisterRISCV = RegisterRISCV::X27;
pub const T3: RegisterRISCV = RegisterRISCV::X28;
pub const T4: RegisterRISCV = RegisterRISCV::X29;
pub const T5: RegisterRISCV = RegisterRISCV::X30;
pub const T6: RegisterRISCV = RegisterRISCV::X31;
pub const FT0: RegisterRISCV = RegisterRISCV::F0;
pub const FT1: RegisterRISCV = RegisterRISCV::F1;
pub const FT2: RegisterRISCV = RegisterRISCV::F2;
pub const FT3: RegisterRISCV = RegisterRISCV::F3;
pub const FT4: RegisterRISCV = RegisterRISCV::F4;
pub const FT5: RegisterRISCV = RegisterRISCV::F5;
pub const FT6: RegisterRISCV = RegisterRISCV::F6;
pub const FT7: RegisterRISCV = RegisterRISCV::F7;
pub const FS0: RegisterRISCV = RegisterRISCV::F8;
pub const FS1: RegisterRISCV = RegisterRISCV::F9;
pub const FA0: RegisterRISCV = RegisterRISCV::F10;
pub const FA1: RegisterRISCV = RegisterRISCV::F11;
pub const FA2: RegisterRISCV = RegisterRISCV::F12;
pub const FA3: RegisterRISCV = RegisterRISCV::F13;
pub const FA4: RegisterRISCV = RegisterRISCV::F14;
pub const FA5: RegisterRISCV = RegisterRISCV::F15;
pub const FA6: RegisterRISCV = RegisterRISCV::F16;
pub const FA7: RegisterRISCV = RegisterRISCV::F17;
pub const FS2: RegisterRISCV = RegisterRISCV::F18;
pub const FS3: RegisterRISCV = RegisterRISCV::F19;
pub const FS4: RegisterRISCV = RegisterRISCV::F20;
pub const FS5: RegisterRISCV = RegisterRISCV::F21;
pub const FS6: RegisterRISCV = RegisterRISCV::F22;
pub const FS7: RegisterRISCV = RegisterRISCV::F23;
pub const FS8: RegisterRISCV = RegisterRISCV::F24;
pub const FS9: RegisterRISCV = RegisterRISCV::F25;
pub const FS10: RegisterRISCV = RegisterRISCV::F26;
pub const FS11: RegisterRISCV = RegisterRISCV::F27;
pub const FT8: RegisterRISCV = RegisterRISCV::F28;
pub const FT9: RegisterRISCV = RegisterRISCV::F29;
pub const FT10: RegisterRISCV = RegisterRISCV::F30;
pub const FT11: RegisterRISCV = RegisterRISCV::F31;
}

11
bindings/rust/src/sparc.rs
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@ -1,3 +1,5 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
// SPARC registers // SPARC registers
#[repr(C)] #[repr(C)]
#[derive(PartialEq, Debug, Clone, Copy)] #[derive(PartialEq, Debug, Clone, Copy)]
@ -91,4 +93,13 @@ pub enum RegisterSPARC {
Y = 86, Y = 86,
XCC = 87, XCC = 87,
PC = 88, PC = 88,
ENDING = 89,
}
impl RegisterSPARC {
// alias registers
// (assoc) O6 = 84,
// (assoc) I6 = 67,
pub const O6: RegisterSPARC = RegisterSPARC::SP;
pub const I6: RegisterSPARC = RegisterSPARC::FP;
} }

12
bindings/rust/src/unicorn_const.rs
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@ -1,11 +1,11 @@
#![allow(non_camel_case_types)] #![allow(non_camel_case_types)]
use bitflags::bitflags; use bitflags::bitflags;
pub const API_MAJOR: u64 = 1; pub const API_MAJOR: u64 = 2;
pub const API_MINOR: u64 = 0; pub const API_MINOR: u64 = 0;
pub const VERSION_MAJOR: u64 = 1; pub const VERSION_MAJOR: u64 = 2;
pub const VERSION_MINOR: u64 = 0; pub const VERSION_MINOR: u64 = 0;
pub const VERSION_EXTRA: u64 = 2; pub const VERSION_EXTRA: u64 = 0;
pub const SECOND_SCALE: u64 = 1_000_000; pub const SECOND_SCALE: u64 = 1_000_000;
pub const MILISECOND_SCALE: u64 = 1_000; pub const MILISECOND_SCALE: u64 = 1_000;
@ -93,6 +93,7 @@ pub enum Query {
MODE = 1, MODE = 1,
PAGE_SIZE = 2, PAGE_SIZE = 2,
ARCH = 3, ARCH = 3,
TIMEOUT = 4,
} }
bitflags! { bitflags! {
@ -124,7 +125,8 @@ pub enum Arch {
PPC = 5, PPC = 5,
SPARC = 6, SPARC = 6,
M68K = 7, M68K = 7,
MAX = 8, RISCV = 8,
MAX = 9,
} }
bitflags! { bitflags! {
@ -154,5 +156,7 @@ bitflags! {
const SPARC32 = Self::MIPS32.bits; const SPARC32 = Self::MIPS32.bits;
const SPARC64 = Self::MIPS64.bits; const SPARC64 = Self::MIPS64.bits;
const V9 = Self::THUMB.bits; const V9 = Self::THUMB.bits;
const RISCV32 = Self::MIPS32.bits;
const RISCV64 = Self::MIPS64.bits;
} }
} }

486
bindings/rust/src/x86.rs
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@ -1,257 +1,245 @@
#![allow(non_camel_case_types)]
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
// X86 registers // X86 registers
#[repr(C)] #[repr(C)]
#[derive(PartialEq, Debug, Clone, Copy)] #[derive(PartialEq, Debug, Clone, Copy)]
pub enum RegisterX86 { pub enum RegisterX86 {
INVALID = 0, INVALID = 0,
AH, AH = 1,
AL, AL = 2,
AX, AX = 3,
BH, BH = 4,
BL, BL = 5,
BP, BP = 6,
BPL, BPL = 7,
BX, BX = 8,
CH, CH = 9,
CL, CL = 10,
CS, CS = 11,
CX, CX = 12,
DH, DH = 13,
DI, DI = 14,
DIL, DIL = 15,
DL, DL = 16,
DS, DS = 17,
DX, DX = 18,
EAX, EAX = 19,
EBP, EBP = 20,
EBX, EBX = 21,
ECX, ECX = 22,
EDI, EDI = 23,
EDX, EDX = 24,
EFLAGS, EFLAGS = 25,
EIP, EIP = 26,
EIZ, ES = 27,
ES, ESI = 28,
ESI, ESP = 29,
ESP, FPSW = 30,
FPSW, FS = 31,
FS, GS = 32,
GS, IP = 33,
IP, RAX = 34,
RAX, RBP = 35,
RBP, RBX = 36,
RBX, RCX = 37,
RCX, RDI = 38,
RDI, RDX = 39,
RDX, RIP = 40,
RIP, RSI = 41,
RIZ, RSP = 42,
RSI, SI = 43,
RSP, SIL = 44,
SI, SP = 45,
SIL, SPL = 46,
SP, SS = 47,
SPL, CR0 = 48,
SS, CR1 = 49,
CR0, CR2 = 50,
CR1, CR3 = 51,
CR2, CR4 = 52,
CR3, CR8 = 53,
CR4, DR0 = 54,
CR5, DR1 = 55,
CR6, DR2 = 56,
CR7, DR3 = 57,
CR8, DR4 = 58,
CR9, DR5 = 59,
CR10, DR6 = 60,
CR11, DR7 = 61,
CR12, FP0 = 62,
CR13, FP1 = 63,
CR14, FP2 = 64,
CR15, FP3 = 65,
DR0, FP4 = 66,
DR1, FP5 = 67,
DR2, FP6 = 68,
DR3, FP7 = 69,
DR4, K0 = 70,
DR5, K1 = 71,
DR6, K2 = 72,
DR7, K3 = 73,
DR8, K4 = 74,
DR9, K5 = 75,
DR10, K6 = 76,
DR11, K7 = 77,
DR12, MM0 = 78,
DR13, MM1 = 79,
DR14, MM2 = 80,
DR15, MM3 = 81,
FP0, MM4 = 82,
FP1, MM5 = 83,
FP2, MM6 = 84,
FP3, MM7 = 85,
FP4, R8 = 86,
FP5, R9 = 87,
FP6, R10 = 88,
FP7, R11 = 89,
K0, R12 = 90,
K1, R13 = 91,
K2, R14 = 92,
K3, R15 = 93,
K4, ST0 = 94,
K5, ST1 = 95,
K6, ST2 = 96,
K7, ST3 = 97,
MM0, ST4 = 98,
MM1, ST5 = 99,
MM2, ST6 = 100,
MM3, ST7 = 101,
MM4, XMM0 = 102,
MM5, XMM1 = 103,
MM6, XMM2 = 104,
MM7, XMM3 = 105,
R8, XMM4 = 106,
R9, XMM5 = 107,
R10, XMM6 = 108,
R11, XMM7 = 109,
R12, XMM8 = 110,
R13, XMM9 = 111,
R14, XMM10 = 112,
R15, XMM11 = 113,
ST0, XMM12 = 114,
ST1, XMM13 = 115,
ST2, XMM14 = 116,
ST3, XMM15 = 117,
ST4, XMM16 = 118,
ST5, XMM17 = 119,
ST6, XMM18 = 120,
ST7, XMM19 = 121,
XMM0, XMM20 = 122,
XMM1, XMM21 = 123,
XMM2, XMM22 = 124,
XMM3, XMM23 = 125,
XMM4, XMM24 = 126,
XMM5, XMM25 = 127,
XMM6, XMM26 = 128,
XMM7, XMM27 = 129,
XMM8, XMM28 = 130,
XMM9, XMM29 = 131,
XMM10, XMM30 = 132,
XMM11, XMM31 = 133,
XMM12, YMM0 = 134,
XMM13, YMM1 = 135,
XMM14, YMM2 = 136,
XMM15, YMM3 = 137,
XMM16, YMM4 = 138,
XMM17, YMM5 = 139,
XMM18, YMM6 = 140,
XMM19, YMM7 = 141,
XMM20, YMM8 = 142,
XMM21, YMM9 = 143,
XMM22, YMM10 = 144,
XMM23, YMM11 = 145,
XMM24, YMM12 = 146,
XMM25, YMM13 = 147,
XMM26, YMM14 = 148,
XMM27, YMM15 = 149,
XMM28, YMM16 = 150,
XMM29, YMM17 = 151,
XMM30, YMM18 = 152,
XMM31, YMM19 = 153,
YMM0, YMM20 = 154,
YMM1, YMM21 = 155,
YMM2, YMM22 = 156,
YMM3, YMM23 = 157,
YMM4, YMM24 = 158,
YMM5, YMM25 = 159,
YMM6, YMM26 = 160,
YMM7, YMM27 = 161,
YMM8, YMM28 = 162,
YMM9, YMM29 = 163,
YMM10, YMM30 = 164,
YMM11, YMM31 = 165,
YMM12, ZMM0 = 166,
YMM13, ZMM1 = 167,
YMM14, ZMM2 = 168,
YMM15, ZMM3 = 169,
YMM16, ZMM4 = 170,
YMM17, ZMM5 = 171,
YMM18, ZMM6 = 172,
YMM19, ZMM7 = 173,
YMM20, ZMM8 = 174,
YMM21, ZMM9 = 175,
YMM22, ZMM10 = 176,
YMM23, ZMM11 = 177,
YMM24, ZMM12 = 178,
YMM25, ZMM13 = 179,
YMM26, ZMM14 = 180,
YMM27, ZMM15 = 181,
YMM28, ZMM16 = 182,
YMM29, ZMM17 = 183,
YMM30, ZMM18 = 184,
YMM31, ZMM19 = 185,
ZMM0, ZMM20 = 186,
ZMM1, ZMM21 = 187,
ZMM2, ZMM22 = 188,
ZMM3, ZMM23 = 189,
ZMM4, ZMM24 = 190,
ZMM5, ZMM25 = 191,
ZMM6, ZMM26 = 192,
ZMM7, ZMM27 = 193,
ZMM8, ZMM28 = 194,
ZMM9, ZMM29 = 195,
ZMM10, ZMM30 = 196,
ZMM11, ZMM31 = 197,
ZMM12, R8B = 198,
ZMM13, R9B = 199,
ZMM14, R10B = 200,
ZMM15, R11B = 201,
ZMM16, R12B = 202,
ZMM17, R13B = 203,
ZMM18, R14B = 204,
ZMM19, R15B = 205,
ZMM20, R8D = 206,
ZMM21, R9D = 207,
ZMM22, R10D = 208,
ZMM23, R11D = 209,
ZMM24, R12D = 210,
ZMM25, R13D = 211,
ZMM26, R14D = 212,
ZMM27, R15D = 213,
ZMM28, R8W = 214,
ZMM29, R9W = 215,
ZMM30, R10W = 216,
ZMM31, R11W = 217,
R8B, R12W = 218,
R9B, R13W = 219,
R10B, R14W = 220,
R11B, R15W = 221,
R12B, IDTR = 222,
R13B, GDTR = 223,
R14B, LDTR = 224,
R15B, TR = 225,
R8D, FPCW = 226,
R9D, FPTAG = 227,
R10D, MSR = 228,
R11D, MXCSR = 229,
R12D, FS_BASE = 230,
R13D, GS_BASE = 231,
R14D, FLAGS = 232,
R15D, RFLAGS = 233,
R8W, ENDING = 234,
R9W,
R10W,
R11W,
R12W,
R13W,
R14W,
R15W,
IDTR,
GDTR,
LDTR,
TR,
FPCW,
FPTAG,
MSR,
MXCSR,
} }
#[repr(C)] #[repr(C)]

24
bindings/rust/tests/unicorn.rs
View File

@ -1,11 +1,9 @@
#![deny(rust_2018_idioms)]
use std::cell::RefCell; use std::cell::RefCell;
use std::rc::Rc; use std::rc::Rc;
use unicorn::unicorn_const::{uc_error, Arch, HookType, MemType, Mode, Permission, SECOND_SCALE}; use unicorn::unicorn_const::{uc_error, Arch, HookType, MemType, Mode, Permission, SECOND_SCALE};
use unicorn::{InsnSysX86, RegisterARM, RegisterMIPS, RegisterPPC, RegisterX86}; use unicorn::{InsnSysX86, RegisterARM, RegisterMIPS, RegisterPPC, RegisterX86};
pub static X86_REGISTERS: [RegisterX86; 145] = [ pub static X86_REGISTERS: [RegisterX86; 125] = [
RegisterX86::AH, RegisterX86::AH,
RegisterX86::AL, RegisterX86::AL,
RegisterX86::AX, RegisterX86::AX,
@ -32,7 +30,6 @@ pub static X86_REGISTERS: [RegisterX86; 145] = [
RegisterX86::EDX, RegisterX86::EDX,
RegisterX86::EFLAGS, RegisterX86::EFLAGS,
RegisterX86::EIP, RegisterX86::EIP,
RegisterX86::EIZ,
RegisterX86::ES, RegisterX86::ES,
RegisterX86::ESI, RegisterX86::ESI,
RegisterX86::ESP, RegisterX86::ESP,
@ -47,7 +44,6 @@ pub static X86_REGISTERS: [RegisterX86; 145] = [
RegisterX86::RDI, RegisterX86::RDI,
RegisterX86::RDX, RegisterX86::RDX,
RegisterX86::RIP, RegisterX86::RIP,
RegisterX86::RIZ,
RegisterX86::RSI, RegisterX86::RSI,
RegisterX86::RSP, RegisterX86::RSP,
RegisterX86::SI, RegisterX86::SI,
@ -60,17 +56,7 @@ pub static X86_REGISTERS: [RegisterX86; 145] = [
RegisterX86::CR2, RegisterX86::CR2,
RegisterX86::CR3, RegisterX86::CR3,
RegisterX86::CR4, RegisterX86::CR4,
RegisterX86::CR5,
RegisterX86::CR6,
RegisterX86::CR7,
RegisterX86::CR8, RegisterX86::CR8,
RegisterX86::CR9,
RegisterX86::CR10,
RegisterX86::CR11,
RegisterX86::CR12,
RegisterX86::CR13,
RegisterX86::CR14,
RegisterX86::CR15,
RegisterX86::DR0, RegisterX86::DR0,
RegisterX86::DR1, RegisterX86::DR1,
RegisterX86::DR2, RegisterX86::DR2,
@ -79,14 +65,6 @@ pub static X86_REGISTERS: [RegisterX86; 145] = [
RegisterX86::DR5, RegisterX86::DR5,
RegisterX86::DR6, RegisterX86::DR6,
RegisterX86::DR7, RegisterX86::DR7,
RegisterX86::DR8,
RegisterX86::DR9,
RegisterX86::DR10,
RegisterX86::DR11,
RegisterX86::DR12,
RegisterX86::DR13,
RegisterX86::DR14,
RegisterX86::DR15,
RegisterX86::FP0, RegisterX86::FP0,
RegisterX86::FP1, RegisterX86::FP1,
RegisterX86::FP2, RegisterX86::FP2,