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ea9c7425b0
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Fix the wrong PC when arm translation fectches unmapped memory
This behavior keeps the same with Unicorn1, though, different from arm doc
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2022-01-16 16:42:38 +01:00 |
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6ed2214399
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Rebuilt hflags when swithing modes
Or we may get the wrong mode during translation
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2022-01-14 19:37:48 +01:00 |
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36afa1022c
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More PPC registers
Add FPR0-31, CR0-7, LR, CTR, MSR, XER, FPSCR for PPC
Add a test for ppc32 float point
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2022-01-10 15:16:10 +01:00 |
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e84a5c44e9
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Add a test for arm mrc instruction (also for coproc)
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2022-01-05 21:57:32 +01:00 |
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8e70f3e524
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Format code
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2022-01-05 21:56:58 +01:00 |
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b8817518ae
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Add a test for arm64 pac extension
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2022-01-05 20:02:21 +01:00 |
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3f64491fda
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Add further test for arm system mode transition
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2022-01-05 19:38:02 +01:00 |
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73149f3616
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Fix test case
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2022-01-04 20:54:52 +01:00 |
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7dc858d03d
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Add a test for arm privilege escalation
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2022-01-04 20:30:07 +01:00 |
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cddc9cf2ed
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Fix arm post init
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2021-12-25 00:16:51 +01:00 |
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5b3a9e1024
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Add test for arm v8
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2021-12-24 23:45:57 +01:00 |
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4f73d75ea8
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Fix #1500
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2021-12-23 21:46:27 +01:00 |
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ef6f8a2427
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Fix x86 CPUID
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2021-12-22 23:39:41 +01:00 |
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7bb0abb977
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Format
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2021-12-22 20:37:15 +01:00 |
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7bb756249a
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Better design of cpuid instruction hook
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2021-12-22 20:36:56 +01:00 |
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033e79abac
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Added cache flush after code patching in unit tests for arm64 and riscv
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2021-12-17 14:55:08 +01:00 |
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549274f44c
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Code patching tests for riscv and arm64
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2021-12-10 15:27:54 +01:00 |
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8a0ca8715e
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Fix SR read/write and a test
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2021-12-04 23:22:28 +01:00 |
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221cde18df
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Write CPSR as it is initiated from instructions to allow regs switch
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2021-11-24 17:10:51 +01:00 |
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78e0ddbc4d
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Fix mmio unmap
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2021-11-24 00:18:19 +01:00 |
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4ed1c4cff9
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Fix test name typo
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2021-11-23 23:24:53 +01:00 |
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3e2580ef9e
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Add test case for #1497
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2021-11-23 22:47:20 +01:00 |
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e11cc16e54
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Implement high-resolution clock for mingw64 in test_ctl
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2021-11-23 14:15:18 +01:00 |
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ccfb66611f
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Move test to test_mem
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2021-11-23 00:41:49 +01:00 |
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b35dbb90b2
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Add test case for #1495
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2021-11-22 18:48:16 +01:00 |
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907ec5095d
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Fix a stackoverflow in tests
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2021-11-21 19:28:45 +01:00 |
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fc467edbc6
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Fix 32bit target getting wrong offset for mmio
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2021-11-16 22:40:57 +01:00 |
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247ffbe0e8
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Support nested uc_emu_start calls
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2021-11-16 21:07:03 +01:00 |
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640251e1aa
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Leave out size parameter in callback
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2021-11-09 00:21:34 +01:00 |
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35017a614f
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Slightly change UC_CTL_TB_REMOVE_CACHE
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2021-11-08 22:09:33 +01:00 |
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e836b62e01
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Minor fix for uc_ctl
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2021-11-08 20:40:02 +01:00 |
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2f61592ff9
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Fix uc_mem_protect
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2021-11-07 20:37:58 +01:00 |
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c6fdbb3735
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Add RISCV CSR registers
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2021-11-07 20:36:04 +01:00 |
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01d7e454b7
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Fix typo
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2021-11-04 20:59:07 +01:00 |
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3aa2788586
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Format
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2021-11-04 18:39:52 +01:00 |
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dfbffa44ec
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Support changing cpu model for ARM
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2021-11-04 18:37:10 +01:00 |
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3e4b4af7d3
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Support change page size
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2021-11-04 17:03:30 +01:00 |
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67e2386da6
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Add test and close #1477
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2021-11-03 21:40:13 +01:00 |
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1a82248292
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Add test for #992
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2021-11-03 21:17:57 +01:00 |
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6b5529fcb7
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Merge pull request #1458 from bet4it/patch
Port some patches from Unicorn1 to Unicorn2
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2021-11-03 20:59:42 +01:00 |
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9818840f4e
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Add tests for UC_HOOK_TCG_OPCODE
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2021-11-03 20:56:45 +01:00 |
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58edb2abe7
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Format
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2021-11-03 13:28:12 +01:00 |
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09aa0f944f
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Merge QDucasse:riscv_extension_d
Fix and close #1469
Fix test for riscv float points
Fix the riscv cpu config we left out
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2021-11-03 13:20:46 +01:00 |
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eb75d459f0
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Add a regression test for invalidating empty TB and have a better solution
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2021-11-03 01:07:06 +01:00 |
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aaf340d9e4
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Merge branch 'dev' into patch
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2021-11-02 18:36:22 +08:00 |
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b7e82d460c
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Expose more TB related stuff
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2021-11-01 22:11:43 +01:00 |
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14e175394b
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Fix Win32 time function for test_ctl
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2021-11-01 19:43:30 +01:00 |
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9704618595
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Fix test for Android due to clock() not working
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2021-11-01 15:33:36 +01:00 |
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cee44b0464
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Add tests and samples to show how to control TB cache
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2021-11-01 14:46:01 +01:00 |
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fb45b287ba
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Add multiple exits mechanism and tests&samples
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2021-11-01 14:00:43 +01:00 |
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