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47097b55b7
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Fix #1520
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2022-01-04 21:01:20 +01:00 |
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085ee07c73
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No more hard-coded cpu models
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2021-12-30 01:05:10 +01:00 |
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cddc9cf2ed
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Fix arm post init
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2021-12-25 00:16:51 +01:00 |
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4f73d75ea8
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Fix #1500
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2021-12-23 21:46:27 +01:00 |
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ef6f8a2427
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Fix x86 CPUID
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2021-12-22 23:39:41 +01:00 |
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7bb756249a
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Better design of cpuid instruction hook
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2021-12-22 20:36:56 +01:00 |
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8a0ca8715e
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Fix SR read/write and a test
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2021-12-04 23:22:28 +01:00 |
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d204dc6374
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Added SR to M68K reg_read and reg_write (#1507)
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2021-12-02 14:12:49 +08:00 |
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221cde18df
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Write CPSR as it is initiated from instructions to allow regs switch
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2021-11-24 17:10:51 +01:00 |
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78e0ddbc4d
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Fix mmio unmap
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2021-11-24 00:18:19 +01:00 |
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c733bbada3
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Fix wrong offset used in split_region
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2021-11-23 23:22:53 +01:00 |
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c1c5f72918
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Fix the sizemask for inline hooking
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2021-11-23 21:18:21 +01:00 |
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7a1de17f37
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Fix UC_HOOK_EDGE_GENERATED to work with indirect jump
For an indirect jump (lookup_tb_ptr), last_tb would be NULL
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2021-11-23 00:25:55 +01:00 |
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083ccf160b
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Use fprintf
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2021-11-22 21:22:21 +01:00 |
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87a391d549
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Inline uc_tracecode when there is only exactly one hook
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2021-11-21 16:44:39 +01:00 |
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c1106b811b
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Fix a memory leak in mmio
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2021-11-16 22:44:03 +01:00 |
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fc467edbc6
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Fix 32bit target getting wrong offset for mmio
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2021-11-16 22:40:57 +01:00 |
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247ffbe0e8
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Support nested uc_emu_start calls
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2021-11-16 21:07:03 +01:00 |
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43c643d4af
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Fix #1488
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2021-11-16 09:41:21 +01:00 |
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7e244f87b4
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Fix UC_HOOK_EDGE_GENERATED implementation
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2021-11-11 22:15:15 +01:00 |
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23ef5da491
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Merge pull request #1481 from bet4it/cp15
Restore cp15 registers
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2021-11-09 16:50:31 +01:00 |
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acaed986b5
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Restore cp15 registers
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2021-11-09 13:13:08 +08:00 |
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640251e1aa
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Leave out size parameter in callback
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2021-11-09 00:21:34 +01:00 |
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2f61592ff9
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Fix uc_mem_protect
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2021-11-07 20:37:58 +01:00 |
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c6fdbb3735
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Add RISCV CSR registers
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2021-11-07 20:36:04 +01:00 |
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7268c2a19b
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mips: support reading and writing of hi/lo regs
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2021-11-07 20:27:02 +01:00 |
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94a82ed94d
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Ensure JIT protection is disabled when generating TB
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2021-11-07 20:23:25 +01:00 |
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613ddf0985
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Format
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2021-11-04 19:58:44 +01:00 |
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871de4ad65
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Split mips cpu to 32 and 64
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2021-11-04 19:58:32 +01:00 |
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0555095388
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Support changing cpu model for ppc
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2021-11-04 19:53:02 +01:00 |
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e5a2eae173
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Add comment for default cpu model
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2021-11-04 19:22:50 +01:00 |
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64452e249d
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Support changing cpu model for sparc
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2021-11-04 19:22:08 +01:00 |
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b0280f5e55
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Support changing cpu model for m68k
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2021-11-04 19:16:35 +01:00 |
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172a2fbe6d
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Support changing cpu model for riscv
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2021-11-04 19:13:53 +01:00 |
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435ac71f47
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Support changing cpu model for x86
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2021-11-04 19:10:29 +01:00 |
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837c3be347
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Support changing cpu model for MIPS
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2021-11-04 19:05:56 +01:00 |
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dfbffa44ec
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Support changing cpu model for ARM
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2021-11-04 18:37:10 +01:00 |
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3e4b4af7d3
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Support change page size
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2021-11-04 17:03:30 +01:00 |
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3ead1731fe
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Also instrument sub2
In this case, users don't need to care about the stuble difference inside tcg opcode
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2021-11-03 23:48:09 +01:00 |
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67e2386da6
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Add test and close #1477
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2021-11-03 21:40:13 +01:00 |
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6b5529fcb7
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Merge pull request #1458 from bet4it/patch
Port some patches from Unicorn1 to Unicorn2
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2021-11-03 20:59:42 +01:00 |
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9818840f4e
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Add tests for UC_HOOK_TCG_OPCODE
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2021-11-03 20:56:45 +01:00 |
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09aa0f944f
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Merge QDucasse:riscv_extension_d
Fix and close #1469
Fix test for riscv float points
Fix the riscv cpu config we left out
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2021-11-03 13:20:46 +01:00 |
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bcf85be86d
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Add a new hook type UC_HOOK_TCG_OPCODE
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2021-11-03 01:46:24 +01:00 |
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eb75d459f0
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Add a regression test for invalidating empty TB and have a better solution
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2021-11-03 01:07:06 +01:00 |
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aaf340d9e4
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Merge branch 'dev' into patch
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2021-11-02 18:36:22 +08:00 |
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c11b9aa5c3
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Add a new hook type UC_HOOK_EDGE_GENERATED and corresponding sample
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2021-11-01 23:27:35 +01:00 |
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b7e82d460c
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Expose more TB related stuff
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2021-11-01 22:11:43 +01:00 |
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6c3960242b
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Format unicorn_arm and unicorn_aarch64
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2021-11-01 10:17:58 +01:00 |
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0a3e46bf4f
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Format
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2021-11-01 09:41:25 +01:00 |
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