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c6fdbb3735
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Add RISCV CSR registers
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2021-11-07 20:36:04 +01:00 |
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7268c2a19b
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mips: support reading and writing of hi/lo regs
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2021-11-07 20:27:02 +01:00 |
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8732cff287
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add rpath and go.mod
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2021-11-07 20:24:50 +01:00 |
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94a82ed94d
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Ensure JIT protection is disabled when generating TB
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2021-11-07 20:23:25 +01:00 |
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923b4ad3cc
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Update python bindings
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2021-11-04 21:47:30 +01:00 |
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cd02c25802
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Fix bug in remove cache and update comments
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2021-11-04 21:29:55 +01:00 |
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a9bfa0afb0
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Update comments
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2021-11-04 21:22:49 +01:00 |
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96fc0bf6bc
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Fix typo in sample
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2021-11-04 21:10:31 +01:00 |
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01d7e454b7
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Fix typo
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2021-11-04 20:59:07 +01:00 |
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1507f90059
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Fix name typo
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2021-11-04 20:07:01 +01:00 |
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b9c0066a47
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Format and naming
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2021-11-04 20:04:57 +01:00 |
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db90f39ac6
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Generate bindings
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2021-11-04 20:01:19 +01:00 |
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025e32df4a
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Init uc on cpu model read
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2021-11-04 20:00:01 +01:00 |
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613ddf0985
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Format
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2021-11-04 19:58:44 +01:00 |
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871de4ad65
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Split mips cpu to 32 and 64
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2021-11-04 19:58:32 +01:00 |
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0555095388
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Support changing cpu model for ppc
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2021-11-04 19:53:02 +01:00 |
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e5a2eae173
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Add comment for default cpu model
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2021-11-04 19:22:50 +01:00 |
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64452e249d
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Support changing cpu model for sparc
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2021-11-04 19:22:08 +01:00 |
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b0280f5e55
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Support changing cpu model for m68k
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2021-11-04 19:16:35 +01:00 |
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172a2fbe6d
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Support changing cpu model for riscv
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2021-11-04 19:13:53 +01:00 |
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435ac71f47
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Support changing cpu model for x86
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2021-11-04 19:10:29 +01:00 |
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837c3be347
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Support changing cpu model for MIPS
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2021-11-04 19:05:56 +01:00 |
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94d952b410
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Add depreciated in unicorn.h
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2021-11-04 18:44:56 +01:00 |
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937445466b
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Update samples to show the use of uc_ctl
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2021-11-04 18:41:45 +01:00 |
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3aa2788586
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Format
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2021-11-04 18:39:52 +01:00 |
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ebe1f83293
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Initialize UC when reading page size
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2021-11-04 18:39:38 +01:00 |
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dfbffa44ec
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Support changing cpu model for ARM
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2021-11-04 18:37:10 +01:00 |
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28013c13be
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Don't init on page size read
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2021-11-04 18:29:42 +01:00 |
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3e4b4af7d3
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Support change page size
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2021-11-04 17:03:30 +01:00 |
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3ead1731fe
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Also instrument sub2
In this case, users don't need to care about the stuble difference inside tcg opcode
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2021-11-03 23:48:09 +01:00 |
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ad2480f32c
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Enable verbose test output
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2021-11-03 21:44:00 +01:00 |
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67e2386da6
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Add test and close #1477
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2021-11-03 21:40:13 +01:00 |
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1a82248292
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Add test for #992
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2021-11-03 21:17:57 +01:00 |
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3dfec280c7
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Merge and close #1161
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2021-11-03 21:02:48 +01:00 |
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6b5529fcb7
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Merge pull request #1458 from bet4it/patch
Port some patches from Unicorn1 to Unicorn2
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2021-11-03 20:59:42 +01:00 |
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9818840f4e
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Add tests for UC_HOOK_TCG_OPCODE
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2021-11-03 20:56:45 +01:00 |
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58edb2abe7
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Format
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2021-11-03 13:28:12 +01:00 |
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09aa0f944f
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Merge QDucasse:riscv_extension_d
Fix and close #1469
Fix test for riscv float points
Fix the riscv cpu config we left out
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2021-11-03 13:20:46 +01:00 |
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bcf85be86d
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Add a new hook type UC_HOOK_TCG_OPCODE
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2021-11-03 01:46:24 +01:00 |
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eb75d459f0
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Add a regression test for invalidating empty TB and have a better solution
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2021-11-03 01:07:06 +01:00 |
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aaf340d9e4
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Merge branch 'dev' into patch
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2021-11-02 18:36:22 +08:00 |
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c11b9aa5c3
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Add a new hook type UC_HOOK_EDGE_GENERATED and corresponding sample
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2021-11-01 23:27:35 +01:00 |
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b7e82d460c
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Expose more TB related stuff
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2021-11-01 22:11:43 +01:00 |
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14e175394b
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Fix Win32 time function for test_ctl
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2021-11-01 19:43:30 +01:00 |
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9704618595
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Fix test for Android due to clock() not working
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2021-11-01 15:33:36 +01:00 |
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cee44b0464
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Add tests and samples to show how to control TB cache
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2021-11-01 14:46:01 +01:00 |
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fb45b287ba
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Add multiple exits mechanism and tests&samples
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2021-11-01 14:00:43 +01:00 |
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a888835962
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Fix mingw64 and win32 build
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2021-11-01 11:02:44 +01:00 |
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fe3b798ba7
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Remove unused args
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2021-11-01 11:02:31 +01:00 |
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f3cb4feec4
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Fix build on Windows
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2021-11-01 10:39:31 +01:00 |
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