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This commit is contained in:
lazymio
2021-11-04 20:04:57 +01:00
parent db90f39ac6
commit b9c0066a47
56 changed files with 249 additions and 93 deletions
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2
bindings/dotnet/UnicornManaged/Const/Arm.fs
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@ -7,6 +7,8 @@ open System
[<AutoOpen>] [<AutoOpen>]
module Arm = module Arm =
// ARM CPU
let UC_CPU_ARM_926 = 0 let UC_CPU_ARM_926 = 0
let UC_CPU_ARM_946 = 1 let UC_CPU_ARM_946 = 1
let UC_CPU_ARM_1026 = 2 let UC_CPU_ARM_1026 = 2

2
bindings/dotnet/UnicornManaged/Const/Arm64.fs
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@ -7,6 +7,8 @@ open System
[<AutoOpen>] [<AutoOpen>]
module Arm64 = module Arm64 =
// ARM64 CPU
let UC_CPU_AARCH64_A57 = 0 let UC_CPU_AARCH64_A57 = 0
let UC_CPU_AARCH64_A53 = 1 let UC_CPU_AARCH64_A53 = 1
let UC_CPU_AARCH64_A72 = 2 let UC_CPU_AARCH64_A72 = 2

2
bindings/dotnet/UnicornManaged/Const/M68k.fs
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@ -7,6 +7,8 @@ open System
[<AutoOpen>] [<AutoOpen>]
module M68k = module M68k =
// M68K CPU
let UC_CPU_M5206_CPU = 0 let UC_CPU_M5206_CPU = 0
let UC_CPU_M68000_CPU = 1 let UC_CPU_M68000_CPU = 1
let UC_CPU_M68020_CPU = 2 let UC_CPU_M68020_CPU = 2

4
bindings/dotnet/UnicornManaged/Const/Mips.fs
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@ -7,6 +7,8 @@ open System
[<AutoOpen>] [<AutoOpen>]
module Mips = module Mips =
// MIPS32 CPUS
let UC_CPU_MIPS32_4KC = 0 let UC_CPU_MIPS32_4KC = 0
let UC_CPU_MIPS32_4KM = 1 let UC_CPU_MIPS32_4KM = 1
let UC_CPU_MIPS32_4KECR1 = 2 let UC_CPU_MIPS32_4KECR1 = 2
@ -24,6 +26,8 @@ module Mips =
let UC_CPU_MIPS32_MIPS32R6_GENERIC = 14 let UC_CPU_MIPS32_MIPS32R6_GENERIC = 14
let UC_CPU_MIPS32_I7200 = 15 let UC_CPU_MIPS32_I7200 = 15
// MIPS64 CPUS
let UC_CPU_MIPS64_R4000 = 0 let UC_CPU_MIPS64_R4000 = 0
let UC_CPU_MIPS64_VR5432 = 1 let UC_CPU_MIPS64_VR5432 = 1
let UC_CPU_MIPS64_5KC = 2 let UC_CPU_MIPS64_5KC = 2

4
bindings/dotnet/UnicornManaged/Const/Ppc.fs
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@ -7,6 +7,8 @@ open System
[<AutoOpen>] [<AutoOpen>]
module Ppc = module Ppc =
// PPC CPU
let UC_CPU_PPC_401 = 0 let UC_CPU_PPC_401 = 0
let UC_CPU_PPC_401A1 = 1 let UC_CPU_PPC_401A1 = 1
let UC_CPU_PPC_401B2 = 2 let UC_CPU_PPC_401B2 = 2
@ -298,6 +300,8 @@ module Ppc =
let UC_CPU_PPC_7447A_V1_2 = 288 let UC_CPU_PPC_7447A_V1_2 = 288
let UC_CPU_PPC_7457A_V1_2 = 289 let UC_CPU_PPC_7457A_V1_2 = 289
// PPC64 CPU
let UC_CPU_PPC_E5500 = 0 let UC_CPU_PPC_E5500 = 0
let UC_CPU_PPC_E6500 = 1 let UC_CPU_PPC_E6500 = 1
let UC_CPU_PPC_970_V2_2 = 2 let UC_CPU_PPC_970_V2_2 = 2

4
bindings/dotnet/UnicornManaged/Const/Riscv.fs
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@ -7,11 +7,15 @@ open System
[<AutoOpen>] [<AutoOpen>]
module Riscv = module Riscv =
// RISCV32 CPU
let UC_CPU_RISCV32_ANY = 0 let UC_CPU_RISCV32_ANY = 0
let UC_CPU_RISCV32_BASE32 = 1 let UC_CPU_RISCV32_BASE32 = 1
let UC_CPU_RISCV32_SIFIVE_E31 = 2 let UC_CPU_RISCV32_SIFIVE_E31 = 2
let UC_CPU_RISCV32_SIFIVE_U34 = 3 let UC_CPU_RISCV32_SIFIVE_U34 = 3
// RISCV64 CPU
let UC_CPU_RISCV64_ANY = 0 let UC_CPU_RISCV64_ANY = 0
let UC_CPU_RISCV64_BASE64 = 1 let UC_CPU_RISCV64_BASE64 = 1
let UC_CPU_RISCV64_SIFIVE_E51 = 2 let UC_CPU_RISCV64_SIFIVE_E51 = 2

30
bindings/dotnet/UnicornManaged/Const/Sparc.fs
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@ -7,19 +7,23 @@ open System
[<AutoOpen>] [<AutoOpen>]
module Sparc = module Sparc =
let UC_CPU_SPARC_FUJITSU_MB86904 = 0 // SPARC32 CPU
let UC_CPU_SPARC_FUJITSU_MB86907 = 1
let UC_CPU_SPARC_TI_MICROSPARC_I = 2 let UC_CPU_SPARC32_FUJITSU_MB86904 = 0
let UC_CPU_SPARC_TI_MICROSPARC_II = 3 let UC_CPU_SPARC32_FUJITSU_MB86907 = 1
let UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4 let UC_CPU_SPARC32_TI_MICROSPARC_I = 2
let UC_CPU_SPARC_TI_SUPERSPARC_40 = 5 let UC_CPU_SPARC32_TI_MICROSPARC_II = 3
let UC_CPU_SPARC_TI_SUPERSPARC_50 = 6 let UC_CPU_SPARC32_TI_MICROSPARC_IIEP = 4
let UC_CPU_SPARC_TI_SUPERSPARC_51 = 7 let UC_CPU_SPARC32_TI_SUPERSPARC_40 = 5
let UC_CPU_SPARC_TI_SUPERSPARC_60 = 8 let UC_CPU_SPARC32_TI_SUPERSPARC_50 = 6
let UC_CPU_SPARC_TI_SUPERSPARC_61 = 9 let UC_CPU_SPARC32_TI_SUPERSPARC_51 = 7
let UC_CPU_SPARC_TI_SUPERSPARC_II = 10 let UC_CPU_SPARC32_TI_SUPERSPARC_60 = 8
let UC_CPU_SPARC_LEON2 = 11 let UC_CPU_SPARC32_TI_SUPERSPARC_61 = 9
let UC_CPU_SPARC_LEON3 = 12 let UC_CPU_SPARC32_TI_SUPERSPARC_II = 10
let UC_CPU_SPARC32_LEON2 = 11
let UC_CPU_SPARC32_LEON3 = 12
// SPARC64 CPU
let UC_CPU_SPARC64_FUJITSU = 0 let UC_CPU_SPARC64_FUJITSU = 0
let UC_CPU_SPARC64_FUJITSU_III = 1 let UC_CPU_SPARC64_FUJITSU_III = 1

2
bindings/dotnet/UnicornManaged/Const/X86.fs
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@ -7,6 +7,8 @@ open System
[<AutoOpen>] [<AutoOpen>]
module X86 = module X86 =
// X86 CPU
let UC_CPU_X86_QEMU64 = 0 let UC_CPU_X86_QEMU64 = 0
let UC_CPU_X86_PHENOM = 1 let UC_CPU_X86_PHENOM = 1
let UC_CPU_X86_CORE2DUO = 2 let UC_CPU_X86_CORE2DUO = 2

2
bindings/go/unicorn/arm64_const.go
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@ -2,6 +2,8 @@ package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.go] // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.go]
const ( const (
// ARM64 CPU
CPU_AARCH64_A57 = 0 CPU_AARCH64_A57 = 0
CPU_AARCH64_A53 = 1 CPU_AARCH64_A53 = 1
CPU_AARCH64_A72 = 2 CPU_AARCH64_A72 = 2

2
bindings/go/unicorn/arm_const.go
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@ -2,6 +2,8 @@ package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.go] // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.go]
const ( const (
// ARM CPU
CPU_ARM_926 = 0 CPU_ARM_926 = 0
CPU_ARM_946 = 1 CPU_ARM_946 = 1
CPU_ARM_1026 = 2 CPU_ARM_1026 = 2

2
bindings/go/unicorn/m68k_const.go
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@ -2,6 +2,8 @@ package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.go] // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.go]
const ( const (
// M68K CPU
CPU_M5206_CPU = 0 CPU_M5206_CPU = 0
CPU_M68000_CPU = 1 CPU_M68000_CPU = 1
CPU_M68020_CPU = 2 CPU_M68020_CPU = 2

4
bindings/go/unicorn/mips_const.go
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@ -2,6 +2,8 @@ package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.go] // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.go]
const ( const (
// MIPS32 CPUS
CPU_MIPS32_4KC = 0 CPU_MIPS32_4KC = 0
CPU_MIPS32_4KM = 1 CPU_MIPS32_4KM = 1
CPU_MIPS32_4KECR1 = 2 CPU_MIPS32_4KECR1 = 2
@ -19,6 +21,8 @@ const (
CPU_MIPS32_MIPS32R6_GENERIC = 14 CPU_MIPS32_MIPS32R6_GENERIC = 14
CPU_MIPS32_I7200 = 15 CPU_MIPS32_I7200 = 15
// MIPS64 CPUS
CPU_MIPS64_R4000 = 0 CPU_MIPS64_R4000 = 0
CPU_MIPS64_VR5432 = 1 CPU_MIPS64_VR5432 = 1
CPU_MIPS64_5KC = 2 CPU_MIPS64_5KC = 2

4
bindings/go/unicorn/ppc_const.go
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@ -2,6 +2,8 @@ package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.go] // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.go]
const ( const (
// PPC CPU
CPU_PPC_401 = 0 CPU_PPC_401 = 0
CPU_PPC_401A1 = 1 CPU_PPC_401A1 = 1
CPU_PPC_401B2 = 2 CPU_PPC_401B2 = 2
@ -293,6 +295,8 @@ const (
CPU_PPC_7447A_V1_2 = 288 CPU_PPC_7447A_V1_2 = 288
CPU_PPC_7457A_V1_2 = 289 CPU_PPC_7457A_V1_2 = 289
// PPC64 CPU
CPU_PPC_E5500 = 0 CPU_PPC_E5500 = 0
CPU_PPC_E6500 = 1 CPU_PPC_E6500 = 1
CPU_PPC_970_V2_2 = 2 CPU_PPC_970_V2_2 = 2

4
bindings/go/unicorn/riscv_const.go
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@ -2,11 +2,15 @@ package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.go] // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.go]
const ( const (
// RISCV32 CPU
CPU_RISCV32_ANY = 0 CPU_RISCV32_ANY = 0
CPU_RISCV32_BASE32 = 1 CPU_RISCV32_BASE32 = 1
CPU_RISCV32_SIFIVE_E31 = 2 CPU_RISCV32_SIFIVE_E31 = 2
CPU_RISCV32_SIFIVE_U34 = 3 CPU_RISCV32_SIFIVE_U34 = 3
// RISCV64 CPU
CPU_RISCV64_ANY = 0 CPU_RISCV64_ANY = 0
CPU_RISCV64_BASE64 = 1 CPU_RISCV64_BASE64 = 1
CPU_RISCV64_SIFIVE_E51 = 2 CPU_RISCV64_SIFIVE_E51 = 2

30
bindings/go/unicorn/sparc_const.go
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@ -2,19 +2,23 @@ package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.go] // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.go]
const ( const (
CPU_SPARC_FUJITSU_MB86904 = 0 // SPARC32 CPU
CPU_SPARC_FUJITSU_MB86907 = 1
CPU_SPARC_TI_MICROSPARC_I = 2 CPU_SPARC32_FUJITSU_MB86904 = 0
CPU_SPARC_TI_MICROSPARC_II = 3 CPU_SPARC32_FUJITSU_MB86907 = 1
CPU_SPARC_TI_MICROSPARC_IIEP = 4 CPU_SPARC32_TI_MICROSPARC_I = 2
CPU_SPARC_TI_SUPERSPARC_40 = 5 CPU_SPARC32_TI_MICROSPARC_II = 3
CPU_SPARC_TI_SUPERSPARC_50 = 6 CPU_SPARC32_TI_MICROSPARC_IIEP = 4
CPU_SPARC_TI_SUPERSPARC_51 = 7 CPU_SPARC32_TI_SUPERSPARC_40 = 5
CPU_SPARC_TI_SUPERSPARC_60 = 8 CPU_SPARC32_TI_SUPERSPARC_50 = 6
CPU_SPARC_TI_SUPERSPARC_61 = 9 CPU_SPARC32_TI_SUPERSPARC_51 = 7
CPU_SPARC_TI_SUPERSPARC_II = 10 CPU_SPARC32_TI_SUPERSPARC_60 = 8
CPU_SPARC_LEON2 = 11 CPU_SPARC32_TI_SUPERSPARC_61 = 9
CPU_SPARC_LEON3 = 12 CPU_SPARC32_TI_SUPERSPARC_II = 10
CPU_SPARC32_LEON2 = 11
CPU_SPARC32_LEON3 = 12
// SPARC64 CPU
CPU_SPARC64_FUJITSU = 0 CPU_SPARC64_FUJITSU = 0
CPU_SPARC64_FUJITSU_III = 1 CPU_SPARC64_FUJITSU_III = 1

2
bindings/go/unicorn/x86_const.go
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@ -2,6 +2,8 @@ package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.go] // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.go]
const ( const (
// X86 CPU
CPU_X86_QEMU64 = 0 CPU_X86_QEMU64 = 0
CPU_X86_PHENOM = 1 CPU_X86_PHENOM = 1
CPU_X86_CORE2DUO = 2 CPU_X86_CORE2DUO = 2

2
bindings/java/unicorn/Arm64Const.java
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@ -4,6 +4,8 @@ package unicorn;
public interface Arm64Const { public interface Arm64Const {
// ARM64 CPU
public static final int UC_CPU_AARCH64_A57 = 0; public static final int UC_CPU_AARCH64_A57 = 0;
public static final int UC_CPU_AARCH64_A53 = 1; public static final int UC_CPU_AARCH64_A53 = 1;
public static final int UC_CPU_AARCH64_A72 = 2; public static final int UC_CPU_AARCH64_A72 = 2;

2
bindings/java/unicorn/ArmConst.java
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@ -4,6 +4,8 @@ package unicorn;
public interface ArmConst { public interface ArmConst {
// ARM CPU
public static final int UC_CPU_ARM_926 = 0; public static final int UC_CPU_ARM_926 = 0;
public static final int UC_CPU_ARM_946 = 1; public static final int UC_CPU_ARM_946 = 1;
public static final int UC_CPU_ARM_1026 = 2; public static final int UC_CPU_ARM_1026 = 2;

2
bindings/java/unicorn/M68kConst.java
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@ -4,6 +4,8 @@ package unicorn;
public interface M68kConst { public interface M68kConst {
// M68K CPU
public static final int UC_CPU_M5206_CPU = 0; public static final int UC_CPU_M5206_CPU = 0;
public static final int UC_CPU_M68000_CPU = 1; public static final int UC_CPU_M68000_CPU = 1;
public static final int UC_CPU_M68020_CPU = 2; public static final int UC_CPU_M68020_CPU = 2;

4
bindings/java/unicorn/MipsConst.java
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@ -4,6 +4,8 @@ package unicorn;
public interface MipsConst { public interface MipsConst {
// MIPS32 CPUS
public static final int UC_CPU_MIPS32_4KC = 0; public static final int UC_CPU_MIPS32_4KC = 0;
public static final int UC_CPU_MIPS32_4KM = 1; public static final int UC_CPU_MIPS32_4KM = 1;
public static final int UC_CPU_MIPS32_4KECR1 = 2; public static final int UC_CPU_MIPS32_4KECR1 = 2;
@ -21,6 +23,8 @@ public interface MipsConst {
public static final int UC_CPU_MIPS32_MIPS32R6_GENERIC = 14; public static final int UC_CPU_MIPS32_MIPS32R6_GENERIC = 14;
public static final int UC_CPU_MIPS32_I7200 = 15; public static final int UC_CPU_MIPS32_I7200 = 15;
// MIPS64 CPUS
public static final int UC_CPU_MIPS64_R4000 = 0; public static final int UC_CPU_MIPS64_R4000 = 0;
public static final int UC_CPU_MIPS64_VR5432 = 1; public static final int UC_CPU_MIPS64_VR5432 = 1;
public static final int UC_CPU_MIPS64_5KC = 2; public static final int UC_CPU_MIPS64_5KC = 2;

4
bindings/java/unicorn/PpcConst.java
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@ -4,6 +4,8 @@ package unicorn;
public interface PpcConst { public interface PpcConst {
// PPC CPU
public static final int UC_CPU_PPC_401 = 0; public static final int UC_CPU_PPC_401 = 0;
public static final int UC_CPU_PPC_401A1 = 1; public static final int UC_CPU_PPC_401A1 = 1;
public static final int UC_CPU_PPC_401B2 = 2; public static final int UC_CPU_PPC_401B2 = 2;
@ -295,6 +297,8 @@ public interface PpcConst {
public static final int UC_CPU_PPC_7447A_V1_2 = 288; public static final int UC_CPU_PPC_7447A_V1_2 = 288;
public static final int UC_CPU_PPC_7457A_V1_2 = 289; public static final int UC_CPU_PPC_7457A_V1_2 = 289;
// PPC64 CPU
public static final int UC_CPU_PPC_E5500 = 0; public static final int UC_CPU_PPC_E5500 = 0;
public static final int UC_CPU_PPC_E6500 = 1; public static final int UC_CPU_PPC_E6500 = 1;
public static final int UC_CPU_PPC_970_V2_2 = 2; public static final int UC_CPU_PPC_970_V2_2 = 2;

4
bindings/java/unicorn/RiscvConst.java
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@ -4,11 +4,15 @@ package unicorn;
public interface RiscvConst { public interface RiscvConst {
// RISCV32 CPU
public static final int UC_CPU_RISCV32_ANY = 0; public static final int UC_CPU_RISCV32_ANY = 0;
public static final int UC_CPU_RISCV32_BASE32 = 1; public static final int UC_CPU_RISCV32_BASE32 = 1;
public static final int UC_CPU_RISCV32_SIFIVE_E31 = 2; public static final int UC_CPU_RISCV32_SIFIVE_E31 = 2;
public static final int UC_CPU_RISCV32_SIFIVE_U34 = 3; public static final int UC_CPU_RISCV32_SIFIVE_U34 = 3;
// RISCV64 CPU
public static final int UC_CPU_RISCV64_ANY = 0; public static final int UC_CPU_RISCV64_ANY = 0;
public static final int UC_CPU_RISCV64_BASE64 = 1; public static final int UC_CPU_RISCV64_BASE64 = 1;
public static final int UC_CPU_RISCV64_SIFIVE_E51 = 2; public static final int UC_CPU_RISCV64_SIFIVE_E51 = 2;

30
bindings/java/unicorn/SparcConst.java
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@ -4,19 +4,23 @@ package unicorn;
public interface SparcConst { public interface SparcConst {
public static final int UC_CPU_SPARC_FUJITSU_MB86904 = 0; // SPARC32 CPU
public static final int UC_CPU_SPARC_FUJITSU_MB86907 = 1;
public static final int UC_CPU_SPARC_TI_MICROSPARC_I = 2; public static final int UC_CPU_SPARC32_FUJITSU_MB86904 = 0;
public static final int UC_CPU_SPARC_TI_MICROSPARC_II = 3; public static final int UC_CPU_SPARC32_FUJITSU_MB86907 = 1;
public static final int UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4; public static final int UC_CPU_SPARC32_TI_MICROSPARC_I = 2;
public static final int UC_CPU_SPARC_TI_SUPERSPARC_40 = 5; public static final int UC_CPU_SPARC32_TI_MICROSPARC_II = 3;
public static final int UC_CPU_SPARC_TI_SUPERSPARC_50 = 6; public static final int UC_CPU_SPARC32_TI_MICROSPARC_IIEP = 4;
public static final int UC_CPU_SPARC_TI_SUPERSPARC_51 = 7; public static final int UC_CPU_SPARC32_TI_SUPERSPARC_40 = 5;
public static final int UC_CPU_SPARC_TI_SUPERSPARC_60 = 8; public static final int UC_CPU_SPARC32_TI_SUPERSPARC_50 = 6;
public static final int UC_CPU_SPARC_TI_SUPERSPARC_61 = 9; public static final int UC_CPU_SPARC32_TI_SUPERSPARC_51 = 7;
public static final int UC_CPU_SPARC_TI_SUPERSPARC_II = 10; public static final int UC_CPU_SPARC32_TI_SUPERSPARC_60 = 8;
public static final int UC_CPU_SPARC_LEON2 = 11; public static final int UC_CPU_SPARC32_TI_SUPERSPARC_61 = 9;
public static final int UC_CPU_SPARC_LEON3 = 12; public static final int UC_CPU_SPARC32_TI_SUPERSPARC_II = 10;
public static final int UC_CPU_SPARC32_LEON2 = 11;
public static final int UC_CPU_SPARC32_LEON3 = 12;
// SPARC64 CPU
public static final int UC_CPU_SPARC64_FUJITSU = 0; public static final int UC_CPU_SPARC64_FUJITSU = 0;
public static final int UC_CPU_SPARC64_FUJITSU_III = 1; public static final int UC_CPU_SPARC64_FUJITSU_III = 1;

2
bindings/java/unicorn/X86Const.java
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@ -4,6 +4,8 @@ package unicorn;
public interface X86Const { public interface X86Const {
// X86 CPU
public static final int UC_CPU_X86_QEMU64 = 0; public static final int UC_CPU_X86_QEMU64 = 0;
public static final int UC_CPU_X86_PHENOM = 1; public static final int UC_CPU_X86_PHENOM = 1;
public static final int UC_CPU_X86_CORE2DUO = 2; public static final int UC_CPU_X86_CORE2DUO = 2;

2
bindings/pascal/unicorn/Arm64Const.pas
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@ -5,6 +5,8 @@ unit Arm64Const;
interface interface
const const
// ARM64 CPU
UC_CPU_AARCH64_A57 = 0; UC_CPU_AARCH64_A57 = 0;
UC_CPU_AARCH64_A53 = 1; UC_CPU_AARCH64_A53 = 1;
UC_CPU_AARCH64_A72 = 2; UC_CPU_AARCH64_A72 = 2;

2
bindings/pascal/unicorn/ArmConst.pas
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@ -5,6 +5,8 @@ unit ArmConst;
interface interface
const const
// ARM CPU
UC_CPU_ARM_926 = 0; UC_CPU_ARM_926 = 0;
UC_CPU_ARM_946 = 1; UC_CPU_ARM_946 = 1;
UC_CPU_ARM_1026 = 2; UC_CPU_ARM_1026 = 2;

2
bindings/pascal/unicorn/M68kConst.pas
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@ -5,6 +5,8 @@ unit M68kConst;
interface interface
const const
// M68K CPU
UC_CPU_M5206_CPU = 0; UC_CPU_M5206_CPU = 0;
UC_CPU_M68000_CPU = 1; UC_CPU_M68000_CPU = 1;
UC_CPU_M68020_CPU = 2; UC_CPU_M68020_CPU = 2;

4
bindings/pascal/unicorn/MipsConst.pas
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@ -5,6 +5,8 @@ unit MipsConst;
interface interface
const const
// MIPS32 CPUS
UC_CPU_MIPS32_4KC = 0; UC_CPU_MIPS32_4KC = 0;
UC_CPU_MIPS32_4KM = 1; UC_CPU_MIPS32_4KM = 1;
UC_CPU_MIPS32_4KECR1 = 2; UC_CPU_MIPS32_4KECR1 = 2;
@ -22,6 +24,8 @@ const
UC_CPU_MIPS32_MIPS32R6_GENERIC = 14; UC_CPU_MIPS32_MIPS32R6_GENERIC = 14;
UC_CPU_MIPS32_I7200 = 15; UC_CPU_MIPS32_I7200 = 15;
// MIPS64 CPUS
UC_CPU_MIPS64_R4000 = 0; UC_CPU_MIPS64_R4000 = 0;
UC_CPU_MIPS64_VR5432 = 1; UC_CPU_MIPS64_VR5432 = 1;
UC_CPU_MIPS64_5KC = 2; UC_CPU_MIPS64_5KC = 2;

4
bindings/pascal/unicorn/PpcConst.pas
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@ -5,6 +5,8 @@ unit PpcConst;
interface interface
const const
// PPC CPU
UC_CPU_PPC_401 = 0; UC_CPU_PPC_401 = 0;
UC_CPU_PPC_401A1 = 1; UC_CPU_PPC_401A1 = 1;
UC_CPU_PPC_401B2 = 2; UC_CPU_PPC_401B2 = 2;
@ -296,6 +298,8 @@ const
UC_CPU_PPC_7447A_V1_2 = 288; UC_CPU_PPC_7447A_V1_2 = 288;
UC_CPU_PPC_7457A_V1_2 = 289; UC_CPU_PPC_7457A_V1_2 = 289;
// PPC64 CPU
UC_CPU_PPC_E5500 = 0; UC_CPU_PPC_E5500 = 0;
UC_CPU_PPC_E6500 = 1; UC_CPU_PPC_E6500 = 1;
UC_CPU_PPC_970_V2_2 = 2; UC_CPU_PPC_970_V2_2 = 2;

4
bindings/pascal/unicorn/RiscvConst.pas
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@ -5,11 +5,15 @@ unit RiscvConst;
interface interface
const const
// RISCV32 CPU
UC_CPU_RISCV32_ANY = 0; UC_CPU_RISCV32_ANY = 0;
UC_CPU_RISCV32_BASE32 = 1; UC_CPU_RISCV32_BASE32 = 1;
UC_CPU_RISCV32_SIFIVE_E31 = 2; UC_CPU_RISCV32_SIFIVE_E31 = 2;
UC_CPU_RISCV32_SIFIVE_U34 = 3; UC_CPU_RISCV32_SIFIVE_U34 = 3;
// RISCV64 CPU
UC_CPU_RISCV64_ANY = 0; UC_CPU_RISCV64_ANY = 0;
UC_CPU_RISCV64_BASE64 = 1; UC_CPU_RISCV64_BASE64 = 1;
UC_CPU_RISCV64_SIFIVE_E51 = 2; UC_CPU_RISCV64_SIFIVE_E51 = 2;

30
bindings/pascal/unicorn/SparcConst.pas
View File

@ -5,19 +5,23 @@ unit SparcConst;
interface interface
const const
UC_CPU_SPARC_FUJITSU_MB86904 = 0; // SPARC32 CPU
UC_CPU_SPARC_FUJITSU_MB86907 = 1;
UC_CPU_SPARC_TI_MICROSPARC_I = 2; UC_CPU_SPARC32_FUJITSU_MB86904 = 0;
UC_CPU_SPARC_TI_MICROSPARC_II = 3; UC_CPU_SPARC32_FUJITSU_MB86907 = 1;
UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4; UC_CPU_SPARC32_TI_MICROSPARC_I = 2;
UC_CPU_SPARC_TI_SUPERSPARC_40 = 5; UC_CPU_SPARC32_TI_MICROSPARC_II = 3;
UC_CPU_SPARC_TI_SUPERSPARC_50 = 6; UC_CPU_SPARC32_TI_MICROSPARC_IIEP = 4;
UC_CPU_SPARC_TI_SUPERSPARC_51 = 7; UC_CPU_SPARC32_TI_SUPERSPARC_40 = 5;
UC_CPU_SPARC_TI_SUPERSPARC_60 = 8; UC_CPU_SPARC32_TI_SUPERSPARC_50 = 6;
UC_CPU_SPARC_TI_SUPERSPARC_61 = 9; UC_CPU_SPARC32_TI_SUPERSPARC_51 = 7;
UC_CPU_SPARC_TI_SUPERSPARC_II = 10; UC_CPU_SPARC32_TI_SUPERSPARC_60 = 8;
UC_CPU_SPARC_LEON2 = 11; UC_CPU_SPARC32_TI_SUPERSPARC_61 = 9;
UC_CPU_SPARC_LEON3 = 12; UC_CPU_SPARC32_TI_SUPERSPARC_II = 10;
UC_CPU_SPARC32_LEON2 = 11;
UC_CPU_SPARC32_LEON3 = 12;
// SPARC64 CPU
UC_CPU_SPARC64_FUJITSU = 0; UC_CPU_SPARC64_FUJITSU = 0;
UC_CPU_SPARC64_FUJITSU_III = 1; UC_CPU_SPARC64_FUJITSU_III = 1;

2
bindings/pascal/unicorn/X86Const.pas
View File

@ -5,6 +5,8 @@ unit X86Const;
interface interface
const const
// X86 CPU
UC_CPU_X86_QEMU64 = 0; UC_CPU_X86_QEMU64 = 0;
UC_CPU_X86_PHENOM = 1; UC_CPU_X86_PHENOM = 1;
UC_CPU_X86_CORE2DUO = 2; UC_CPU_X86_CORE2DUO = 2;

2
bindings/python/unicorn/arm64_const.py
View File

@ -1,5 +1,7 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py] # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py]
# ARM64 CPU
UC_CPU_AARCH64_A57 = 0 UC_CPU_AARCH64_A57 = 0
UC_CPU_AARCH64_A53 = 1 UC_CPU_AARCH64_A53 = 1
UC_CPU_AARCH64_A72 = 2 UC_CPU_AARCH64_A72 = 2

2
bindings/python/unicorn/arm_const.py
View File

@ -1,5 +1,7 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py] # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py]
# ARM CPU
UC_CPU_ARM_926 = 0 UC_CPU_ARM_926 = 0
UC_CPU_ARM_946 = 1 UC_CPU_ARM_946 = 1
UC_CPU_ARM_1026 = 2 UC_CPU_ARM_1026 = 2

2
bindings/python/unicorn/m68k_const.py
View File

@ -1,5 +1,7 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py] # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py]
# M68K CPU
UC_CPU_M5206_CPU = 0 UC_CPU_M5206_CPU = 0
UC_CPU_M68000_CPU = 1 UC_CPU_M68000_CPU = 1
UC_CPU_M68020_CPU = 2 UC_CPU_M68020_CPU = 2

4
bindings/python/unicorn/mips_const.py
View File

@ -1,5 +1,7 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py] # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
# MIPS32 CPUS
UC_CPU_MIPS32_4KC = 0 UC_CPU_MIPS32_4KC = 0
UC_CPU_MIPS32_4KM = 1 UC_CPU_MIPS32_4KM = 1
UC_CPU_MIPS32_4KECR1 = 2 UC_CPU_MIPS32_4KECR1 = 2
@ -17,6 +19,8 @@ UC_CPU_MIPS32_P5600 = 13
UC_CPU_MIPS32_MIPS32R6_GENERIC = 14 UC_CPU_MIPS32_MIPS32R6_GENERIC = 14
UC_CPU_MIPS32_I7200 = 15 UC_CPU_MIPS32_I7200 = 15
# MIPS64 CPUS
UC_CPU_MIPS64_R4000 = 0 UC_CPU_MIPS64_R4000 = 0
UC_CPU_MIPS64_VR5432 = 1 UC_CPU_MIPS64_VR5432 = 1
UC_CPU_MIPS64_5KC = 2 UC_CPU_MIPS64_5KC = 2

4
bindings/python/unicorn/ppc_const.py
View File

@ -1,5 +1,7 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.py] # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.py]
# PPC CPU
UC_CPU_PPC_401 = 0 UC_CPU_PPC_401 = 0
UC_CPU_PPC_401A1 = 1 UC_CPU_PPC_401A1 = 1
UC_CPU_PPC_401B2 = 2 UC_CPU_PPC_401B2 = 2
@ -291,6 +293,8 @@ UC_CPU_PPC_7457A_V1_1 = 287
UC_CPU_PPC_7447A_V1_2 = 288 UC_CPU_PPC_7447A_V1_2 = 288
UC_CPU_PPC_7457A_V1_2 = 289 UC_CPU_PPC_7457A_V1_2 = 289
# PPC64 CPU
UC_CPU_PPC_E5500 = 0 UC_CPU_PPC_E5500 = 0
UC_CPU_PPC_E6500 = 1 UC_CPU_PPC_E6500 = 1
UC_CPU_PPC_970_V2_2 = 2 UC_CPU_PPC_970_V2_2 = 2

4
bindings/python/unicorn/riscv_const.py
View File

@ -1,10 +1,14 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py] # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
# RISCV32 CPU
UC_CPU_RISCV32_ANY = 0 UC_CPU_RISCV32_ANY = 0
UC_CPU_RISCV32_BASE32 = 1 UC_CPU_RISCV32_BASE32 = 1
UC_CPU_RISCV32_SIFIVE_E31 = 2 UC_CPU_RISCV32_SIFIVE_E31 = 2
UC_CPU_RISCV32_SIFIVE_U34 = 3 UC_CPU_RISCV32_SIFIVE_U34 = 3
# RISCV64 CPU
UC_CPU_RISCV64_ANY = 0 UC_CPU_RISCV64_ANY = 0
UC_CPU_RISCV64_BASE64 = 1 UC_CPU_RISCV64_BASE64 = 1
UC_CPU_RISCV64_SIFIVE_E51 = 2 UC_CPU_RISCV64_SIFIVE_E51 = 2

30
bindings/python/unicorn/sparc_const.py
View File

@ -1,18 +1,22 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py] # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py]
UC_CPU_SPARC_FUJITSU_MB86904 = 0 # SPARC32 CPU
UC_CPU_SPARC_FUJITSU_MB86907 = 1
UC_CPU_SPARC_TI_MICROSPARC_I = 2 UC_CPU_SPARC32_FUJITSU_MB86904 = 0
UC_CPU_SPARC_TI_MICROSPARC_II = 3 UC_CPU_SPARC32_FUJITSU_MB86907 = 1
UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4 UC_CPU_SPARC32_TI_MICROSPARC_I = 2
UC_CPU_SPARC_TI_SUPERSPARC_40 = 5 UC_CPU_SPARC32_TI_MICROSPARC_II = 3
UC_CPU_SPARC_TI_SUPERSPARC_50 = 6 UC_CPU_SPARC32_TI_MICROSPARC_IIEP = 4
UC_CPU_SPARC_TI_SUPERSPARC_51 = 7 UC_CPU_SPARC32_TI_SUPERSPARC_40 = 5
UC_CPU_SPARC_TI_SUPERSPARC_60 = 8 UC_CPU_SPARC32_TI_SUPERSPARC_50 = 6
UC_CPU_SPARC_TI_SUPERSPARC_61 = 9 UC_CPU_SPARC32_TI_SUPERSPARC_51 = 7
UC_CPU_SPARC_TI_SUPERSPARC_II = 10 UC_CPU_SPARC32_TI_SUPERSPARC_60 = 8
UC_CPU_SPARC_LEON2 = 11 UC_CPU_SPARC32_TI_SUPERSPARC_61 = 9
UC_CPU_SPARC_LEON3 = 12 UC_CPU_SPARC32_TI_SUPERSPARC_II = 10
UC_CPU_SPARC32_LEON2 = 11
UC_CPU_SPARC32_LEON3 = 12
# SPARC64 CPU
UC_CPU_SPARC64_FUJITSU = 0 UC_CPU_SPARC64_FUJITSU = 0
UC_CPU_SPARC64_FUJITSU_III = 1 UC_CPU_SPARC64_FUJITSU_III = 1

2
bindings/python/unicorn/x86_const.py
View File

@ -1,5 +1,7 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py] # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py]
# X86 CPU
UC_CPU_X86_QEMU64 = 0 UC_CPU_X86_QEMU64 = 0
UC_CPU_X86_PHENOM = 1 UC_CPU_X86_PHENOM = 1
UC_CPU_X86_CORE2DUO = 2 UC_CPU_X86_CORE2DUO = 2

2
bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb
View File

@ -2,6 +2,8 @@
module UnicornEngine module UnicornEngine
# ARM64 CPU
UC_CPU_AARCH64_A57 = 0 UC_CPU_AARCH64_A57 = 0
UC_CPU_AARCH64_A53 = 1 UC_CPU_AARCH64_A53 = 1
UC_CPU_AARCH64_A72 = 2 UC_CPU_AARCH64_A72 = 2

2
bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb
View File

@ -2,6 +2,8 @@
module UnicornEngine module UnicornEngine
# ARM CPU
UC_CPU_ARM_926 = 0 UC_CPU_ARM_926 = 0
UC_CPU_ARM_946 = 1 UC_CPU_ARM_946 = 1
UC_CPU_ARM_1026 = 2 UC_CPU_ARM_1026 = 2

2
bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb
View File

@ -2,6 +2,8 @@
module UnicornEngine module UnicornEngine
# M68K CPU
UC_CPU_M5206_CPU = 0 UC_CPU_M5206_CPU = 0
UC_CPU_M68000_CPU = 1 UC_CPU_M68000_CPU = 1
UC_CPU_M68020_CPU = 2 UC_CPU_M68020_CPU = 2

4
bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb
View File

@ -2,6 +2,8 @@
module UnicornEngine module UnicornEngine
# MIPS32 CPUS
UC_CPU_MIPS32_4KC = 0 UC_CPU_MIPS32_4KC = 0
UC_CPU_MIPS32_4KM = 1 UC_CPU_MIPS32_4KM = 1
UC_CPU_MIPS32_4KECR1 = 2 UC_CPU_MIPS32_4KECR1 = 2
@ -19,6 +21,8 @@ module UnicornEngine
UC_CPU_MIPS32_MIPS32R6_GENERIC = 14 UC_CPU_MIPS32_MIPS32R6_GENERIC = 14
UC_CPU_MIPS32_I7200 = 15 UC_CPU_MIPS32_I7200 = 15
# MIPS64 CPUS
UC_CPU_MIPS64_R4000 = 0 UC_CPU_MIPS64_R4000 = 0
UC_CPU_MIPS64_VR5432 = 1 UC_CPU_MIPS64_VR5432 = 1
UC_CPU_MIPS64_5KC = 2 UC_CPU_MIPS64_5KC = 2

4
bindings/ruby/unicorn_gem/lib/unicorn_engine/ppc_const.rb
View File

@ -2,6 +2,8 @@
module UnicornEngine module UnicornEngine
# PPC CPU
UC_CPU_PPC_401 = 0 UC_CPU_PPC_401 = 0
UC_CPU_PPC_401A1 = 1 UC_CPU_PPC_401A1 = 1
UC_CPU_PPC_401B2 = 2 UC_CPU_PPC_401B2 = 2
@ -293,6 +295,8 @@ module UnicornEngine
UC_CPU_PPC_7447A_V1_2 = 288 UC_CPU_PPC_7447A_V1_2 = 288
UC_CPU_PPC_7457A_V1_2 = 289 UC_CPU_PPC_7457A_V1_2 = 289
# PPC64 CPU
UC_CPU_PPC_E5500 = 0 UC_CPU_PPC_E5500 = 0
UC_CPU_PPC_E6500 = 1 UC_CPU_PPC_E6500 = 1
UC_CPU_PPC_970_V2_2 = 2 UC_CPU_PPC_970_V2_2 = 2

4
bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb
View File

@ -2,11 +2,15 @@
module UnicornEngine module UnicornEngine
# RISCV32 CPU
UC_CPU_RISCV32_ANY = 0 UC_CPU_RISCV32_ANY = 0
UC_CPU_RISCV32_BASE32 = 1 UC_CPU_RISCV32_BASE32 = 1
UC_CPU_RISCV32_SIFIVE_E31 = 2 UC_CPU_RISCV32_SIFIVE_E31 = 2
UC_CPU_RISCV32_SIFIVE_U34 = 3 UC_CPU_RISCV32_SIFIVE_U34 = 3
# RISCV64 CPU
UC_CPU_RISCV64_ANY = 0 UC_CPU_RISCV64_ANY = 0
UC_CPU_RISCV64_BASE64 = 1 UC_CPU_RISCV64_BASE64 = 1
UC_CPU_RISCV64_SIFIVE_E51 = 2 UC_CPU_RISCV64_SIFIVE_E51 = 2

30
bindings/ruby/unicorn_gem/lib/unicorn_engine/sparc_const.rb
View File

@ -2,19 +2,23 @@
module UnicornEngine module UnicornEngine
UC_CPU_SPARC_FUJITSU_MB86904 = 0 # SPARC32 CPU
UC_CPU_SPARC_FUJITSU_MB86907 = 1
UC_CPU_SPARC_TI_MICROSPARC_I = 2 UC_CPU_SPARC32_FUJITSU_MB86904 = 0
UC_CPU_SPARC_TI_MICROSPARC_II = 3 UC_CPU_SPARC32_FUJITSU_MB86907 = 1
UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4 UC_CPU_SPARC32_TI_MICROSPARC_I = 2
UC_CPU_SPARC_TI_SUPERSPARC_40 = 5 UC_CPU_SPARC32_TI_MICROSPARC_II = 3
UC_CPU_SPARC_TI_SUPERSPARC_50 = 6 UC_CPU_SPARC32_TI_MICROSPARC_IIEP = 4
UC_CPU_SPARC_TI_SUPERSPARC_51 = 7 UC_CPU_SPARC32_TI_SUPERSPARC_40 = 5
UC_CPU_SPARC_TI_SUPERSPARC_60 = 8 UC_CPU_SPARC32_TI_SUPERSPARC_50 = 6
UC_CPU_SPARC_TI_SUPERSPARC_61 = 9 UC_CPU_SPARC32_TI_SUPERSPARC_51 = 7
UC_CPU_SPARC_TI_SUPERSPARC_II = 10 UC_CPU_SPARC32_TI_SUPERSPARC_60 = 8
UC_CPU_SPARC_LEON2 = 11 UC_CPU_SPARC32_TI_SUPERSPARC_61 = 9
UC_CPU_SPARC_LEON3 = 12 UC_CPU_SPARC32_TI_SUPERSPARC_II = 10
UC_CPU_SPARC32_LEON2 = 11
UC_CPU_SPARC32_LEON3 = 12
# SPARC64 CPU
UC_CPU_SPARC64_FUJITSU = 0 UC_CPU_SPARC64_FUJITSU = 0
UC_CPU_SPARC64_FUJITSU_III = 1 UC_CPU_SPARC64_FUJITSU_III = 1

2
bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb
View File

@ -2,6 +2,8 @@
module UnicornEngine module UnicornEngine
# X86 CPU
UC_CPU_X86_QEMU64 = 0 UC_CPU_X86_QEMU64 = 0
UC_CPU_X86_PHENOM = 1 UC_CPU_X86_PHENOM = 1
UC_CPU_X86_CORE2DUO = 2 UC_CPU_X86_CORE2DUO = 2

1
include/unicorn/arm.h
View File

@ -15,6 +15,7 @@ extern "C" {
#pragma warning(disable : 4201) #pragma warning(disable : 4201)
#endif #endif
//> ARM CPU
typedef enum uc_cpu_arm { typedef enum uc_cpu_arm {
UC_CPU_ARM_926 = 0, UC_CPU_ARM_926 = 0,
UC_CPU_ARM_946, UC_CPU_ARM_946,

1
include/unicorn/arm64.h
View File

@ -15,6 +15,7 @@ extern "C" {
#pragma warning(disable : 4201) #pragma warning(disable : 4201)
#endif #endif
//> ARM64 CPU
typedef enum uc_cpu_aarch64 { typedef enum uc_cpu_aarch64 {
UC_CPU_AARCH64_A57 = 0, UC_CPU_AARCH64_A57 = 0,
UC_CPU_AARCH64_A53, UC_CPU_AARCH64_A53,

1
include/unicorn/m68k.h
View File

@ -15,6 +15,7 @@ extern "C" {
#pragma warning(disable : 4201) #pragma warning(disable : 4201)
#endif #endif
//> M68K CPU
typedef enum uc_cpu_m68k { typedef enum uc_cpu_m68k {
UC_CPU_M5206_CPU = 0, UC_CPU_M5206_CPU = 0,
UC_CPU_M68000_CPU, UC_CPU_M68000_CPU,

2
include/unicorn/mips.h
View File

@ -19,6 +19,7 @@ extern "C" {
#pragma warning(disable : 4201) #pragma warning(disable : 4201)
#endif #endif
//> MIPS32 CPUS
typedef enum uc_cpu_mips32 { typedef enum uc_cpu_mips32 {
UC_CPU_MIPS32_4KC = 0, UC_CPU_MIPS32_4KC = 0,
UC_CPU_MIPS32_4KM, UC_CPU_MIPS32_4KM,
@ -38,6 +39,7 @@ typedef enum uc_cpu_mips32 {
UC_CPU_MIPS32_I7200, UC_CPU_MIPS32_I7200,
} uc_cpu_mips32; } uc_cpu_mips32;
//> MIPS64 CPUS
typedef enum uc_cpu_mips64 { typedef enum uc_cpu_mips64 {
UC_CPU_MIPS64_R4000 = 0, UC_CPU_MIPS64_R4000 = 0,
UC_CPU_MIPS64_VR5432, UC_CPU_MIPS64_VR5432,

2
include/unicorn/ppc.h
View File

@ -15,6 +15,7 @@ extern "C" {
#pragma warning(disable : 4201) #pragma warning(disable : 4201)
#endif #endif
//> PPC CPU
typedef enum uc_cpu_ppc { typedef enum uc_cpu_ppc {
UC_CPU_PPC_401 = 0, UC_CPU_PPC_401 = 0,
UC_CPU_PPC_401A1, UC_CPU_PPC_401A1,
@ -308,6 +309,7 @@ typedef enum uc_cpu_ppc {
UC_CPU_PPC_7457A_V1_2, UC_CPU_PPC_7457A_V1_2,
} uc_cpu_ppc; } uc_cpu_ppc;
//> PPC64 CPU
typedef enum uc_cpu_ppc64 { typedef enum uc_cpu_ppc64 {
UC_CPU_PPC_E5500 = 0, UC_CPU_PPC_E5500 = 0,
UC_CPU_PPC_E6500, UC_CPU_PPC_E6500,

2
include/unicorn/riscv.h
View File

@ -15,6 +15,7 @@ extern "C" {
#pragma warning(disable : 4201) #pragma warning(disable : 4201)
#endif #endif
//> RISCV32 CPU
typedef enum uc_cpu_riscv32 { typedef enum uc_cpu_riscv32 {
UC_CPU_RISCV32_ANY = 0, UC_CPU_RISCV32_ANY = 0,
UC_CPU_RISCV32_BASE32, UC_CPU_RISCV32_BASE32,
@ -22,6 +23,7 @@ typedef enum uc_cpu_riscv32 {
UC_CPU_RISCV32_SIFIVE_U34, UC_CPU_RISCV32_SIFIVE_U34,
} uc_cpu_riscv32; } uc_cpu_riscv32;
//> RISCV64 CPU
typedef enum uc_cpu_riscv64 { typedef enum uc_cpu_riscv64 {
UC_CPU_RISCV64_ANY = 0, UC_CPU_RISCV64_ANY = 0,
UC_CPU_RISCV64_BASE64, UC_CPU_RISCV64_BASE64,

32
include/unicorn/sparc.h
View File

@ -19,22 +19,24 @@ extern "C" {
#pragma warning(disable : 4201) #pragma warning(disable : 4201)
#endif #endif
typedef enum uc_cpu_sparc { //> SPARC32 CPU
UC_CPU_SPARC_FUJITSU_MB86904 = 0, typedef enum uc_cpu_sparc32 {
UC_CPU_SPARC_FUJITSU_MB86907, UC_CPU_SPARC32_FUJITSU_MB86904 = 0,
UC_CPU_SPARC_TI_MICROSPARC_I, UC_CPU_SPARC32_FUJITSU_MB86907,
UC_CPU_SPARC_TI_MICROSPARC_II, UC_CPU_SPARC32_TI_MICROSPARC_I,
UC_CPU_SPARC_TI_MICROSPARC_IIEP, UC_CPU_SPARC32_TI_MICROSPARC_II,
UC_CPU_SPARC_TI_SUPERSPARC_40, UC_CPU_SPARC32_TI_MICROSPARC_IIEP,
UC_CPU_SPARC_TI_SUPERSPARC_50, UC_CPU_SPARC32_TI_SUPERSPARC_40,
UC_CPU_SPARC_TI_SUPERSPARC_51, UC_CPU_SPARC32_TI_SUPERSPARC_50,
UC_CPU_SPARC_TI_SUPERSPARC_60, UC_CPU_SPARC32_TI_SUPERSPARC_51,
UC_CPU_SPARC_TI_SUPERSPARC_61, UC_CPU_SPARC32_TI_SUPERSPARC_60,
UC_CPU_SPARC_TI_SUPERSPARC_II, UC_CPU_SPARC32_TI_SUPERSPARC_61,
UC_CPU_SPARC_LEON2, UC_CPU_SPARC32_TI_SUPERSPARC_II,
UC_CPU_SPARC_LEON3 UC_CPU_SPARC32_LEON2,
} uc_cpu_sparc; UC_CPU_SPARC32_LEON3
} uc_cpu_sparc32;
//> SPARC64 CPU
typedef enum uc_cpu_sparc64 { typedef enum uc_cpu_sparc64 {
UC_CPU_SPARC64_FUJITSU = 0, UC_CPU_SPARC64_FUJITSU = 0,
UC_CPU_SPARC64_FUJITSU_III, UC_CPU_SPARC64_FUJITSU_III,

1
include/unicorn/x86.h
View File

@ -13,6 +13,7 @@ extern "C" {
#include "platform.h" #include "platform.h"
//> X86 CPU
typedef enum uc_cpu_x86 { typedef enum uc_cpu_x86 {
UC_CPU_X86_QEMU64 = 0, UC_CPU_X86_QEMU64 = 0,
UC_CPU_X86_PHENOM, UC_CPU_X86_PHENOM,